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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-04 14:09:33 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-04 14:09:33 +0200 |
| commit | 6edb69b808042eca12d4be7b923833c1dd94681e (patch) | |
| tree | 41a8715ea858bea833a6dec3a65b37663ecd81b9 /tools/perf/scripts/python | |
| parent | f924a4041f4ad6f6772f437596f0249e46edfb79 (diff) | |
| parent | 272a6e2ad164094045af520299b5df3ce1763061 (diff) | |
Merge tag 'clk-renesas-rzg3e-plldsi-tag' into renesas-clk-for-v7.2
clk: renesas: rzg3e: Add support for DSI clocks
RZ/G3E Clock Pulse Generator PLLDSI limits, shared by clock and MIPI DSI
driver source files.
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions