diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-05-05 08:15:38 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-11 10:09:27 +0200 |
| commit | 29c46057d55648d88805e0412deb8729d806bf97 (patch) | |
| tree | d264f23ecbed546b2cd37a34c6e3209eea0eea11 /tools/perf/scripts/python | |
| parent | 9bec6a9dc213aa0134d672f70d6afa363f4b3c88 (diff) | |
clk: renesas: r9a08g046: Add SSIF-2 clocks and resets
Add SSIF-2 clock and reset entries on the RZ/G3L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505071544.8965-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions