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authorVladimir Oltean <vladimir.oltean@nxp.com>2026-06-10 18:19:50 +0300
committerVinod Koul <vkoul@kernel.org>2026-06-11 12:39:47 +0530
commita7dc4e95d31c6bc674b24697aacadf7c6f1cbe6a (patch)
treed4ecc6912a06dbb66472d8d2901466d91f55e772 /tools/perf/scripts/python/stackcollapse.py
parentf124b54b19223c85dabd9421ec622d8256e240de (diff)
dt-bindings: phy: lynx-10g: initial document
Add a schema for the 10G Lynx SerDes. This is very similar to the modern form of the 28G Lynx SerDes, which is very much the intention. There is intentionally no generic fsl,lynx-10g compatible string due to the hardware inability to report its capabilities, despite having a common register map. We allow both forms of #phy-cells = <1> in the top-level provider and #phy-cells = <0> in the per-lane provider for more flexibility to consumers, and because the kernel code is shared with the 28G Lynx which already has that support for compatibility reasons. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260610151952.2141019-15-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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