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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-05-05 08:15:37 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-11 10:09:24 +0200 |
| commit | 9bec6a9dc213aa0134d672f70d6afa363f4b3c88 (patch) | |
| tree | 7b4d4785e78d79752daf5c4e9c7b16eaa3dcfb40 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 7f0c422c7fbfd9294ff9321ada0c63561e5c6ea0 (diff) | |
clk: renesas: r9a08g046: Add RSCI clocks and resets
Add clock and reset entries for the Serial Communications Interfaces
(RSCI) found on the RZ/G3L SoC. This includes various dividers and mux
clocks needed for the four RSCI channels.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505071544.8965-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions