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| author | Bibo Mao <maobibo@loongson.cn> | 2026-06-11 20:46:42 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2026-06-11 20:46:42 +0800 |
| commit | 42985883613cb316d9a1520365ff6c1e07ef5c11 (patch) | |
| tree | 93635adfe89863eda7b3159b93f99b2a4455658d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3179253ad52f9d0e1c44873f0a2a4f0792e7103d (diff) | |
LoongArch: KVM: Add valid bit check when set CSR.ESTAT register
When set CSR.ESTAT register in function _kvm_setcsr(), valid bit check
is added here. Also interrupt CPU_AVEC is checked by msgint feature.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions