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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-04-30 11:08:16 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-07 10:22:20 +0200 |
| commit | 01a20f1c46ed8fdbc9c4c97de60fae1a49f81b48 (patch) | |
| tree | 1aee7130741b751838979d25d4e48a6844df5904 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 6edb69b808042eca12d4be7b923833c1dd94681e (diff) | |
clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks
Add R9A08G046_IA55_PCLK to the critical module clocks list to prevent
the clock from being gated during suspend, as it is required for the
interrupt controller (IA55) to function correctly.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430100838.157306-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions