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| author | Denzeel Oliva <wachiturroxd150@gmail.com> | 2026-05-28 15:09:01 -0500 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2026-05-30 18:50:36 +0200 |
| commit | e11560b050ce867bd7d3ccea138231db54e2250a (patch) | |
| tree | 48e779005aa39ea4fc4a9032e8d178085657f551 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 44984aaf1aa727ff944dd4b72fcf069d08b0056d (diff) | |
clk: samsung: exynos990: Fix PERIC0/1 USI clock types
Use nMUX() for USI and UART user muxes to allow reparenting between
OSC and CMU IP output when changing rates, and use DIV_F() with
CLK_SET_RATE_PARENT on their dividers and gates so rate requests
propagate upward.
Consolidate identical USI parent arrays into shared
mout_peric0_nonbususer_p and mout_peric1_nonbususer_p.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://patch.msgid.link/20260528-perics-usi-v1-1-13a6ee4d1a6f@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions