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authorBiju Das <biju.das.jz@bp.renesas.com>2026-05-05 08:15:39 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2026-05-11 10:09:27 +0200
commit5fcbbc1fcc4fa78bb5a184caa2c32db423676577 (patch)
tree54d7762a2fe8546340ae65e5390f20eb2e72c470 /tools/perf/scripts/python/export-to-postgresql.py
parent29c46057d55648d88805e0412deb8729d806bf97 (diff)
clk: renesas: r9a08g046: Add RSPI clocks and resets
Add clock and reset definitions for the three RSPI (Serial Peripheral Interface) channels on the RZ/G3L (R9A08G046) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505071544.8965-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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