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| author | Yixun Lan <dlan@gentoo.org> | 2025-10-27 21:41:24 +0800 |
|---|---|---|
| committer | Yixun Lan <dlan@gentoo.org> | 2026-01-09 10:29:10 +0800 |
| commit | 3a086236c600739d6653c0405d86aff7d6f03c06 (patch) | |
| tree | 520093bed874c9cabb09d0eb29148033b966a3c9 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | ace73b7e27633ec770cfb24cd4ff42c24815a9aa (diff) | |
clk: spacemit: ccu_pll: add plla type clock
Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different
register layout comparing to previous PPL type. And, It is configured
by swcr1, swcr3 and swcr2 BIT[15:8].
Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions