Merge tag 'mtd/for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull mtd updates from Miquel Raynal:
 "NAND changes:

   - Extend SPI NAND continuous read to Winbond devices, which requires
     numerous changes in the spi-{mem,nand} layers such as the need for
     a secondary read operation template

   - Continuous reads in general have also been enhanced/fixed for
     avoiding potential issues at probe time and at block boundaries

  SPI NOR changes:

   - Big set of cleanups and improvements to the locking support.

     This series contains some cleanups and bug fixes for code and
     documentation around write protection. Then support is added for
     complement locking, which allows finer grained configuration of
     what is considered locked and unlocked. Then complement locking is
     enabled on a bunch of Winbond W25 flashes

   - Fix die erase support on Spansion flashes.

     Die erase is only supported on multi-die flashes, but the die erase
     opcode was set for all. When the opcode is set, it overrides the
     default chip erase opcode which should be used for single-die
     flashes. Only set the opcode on multi-die flashes. Also, the opcode
     was not set on multi-die s28hx-t flashes. Set it so they can use
     die-erase correctly

  General changes:

   - A few drivers and mappings have been removed following SoCs support
     removal

   - And again, there is the usual load of misc improvements and fixes"

* tag 'mtd/for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (63 commits)
  mtd: cfi: Use common error handling code in two functions
  mtd: slram: simplify register_device() cleanup
  mtd: slram: remove failed entries from the device list
  mtd: rawnand: ndfc: use ioread32be/iowrite32be and allow COMPILE_TEST
  mtd: spi-nor: spansion: add die erase support in s28hx-t
  mtd: spi-nor: spansion: use die erase for multi-die devices only
  mtd: spi-nor: winbond: Add W25Q02NWxxIM CMP locking support
  mtd: spi-nor: winbond: Add W25Q01NWxxIM CMP locking support
  mtd: spi-nor: winbond: Add W25Q01NWxxIQ CMP locking support
  mtd: spi-nor: winbond: Add W25H02NWxxAM CMP locking support
  mtd: spi-nor: winbond: Add W25H01NWxxAM CMP locking support
  mtd: spi-nor: winbond: Add W25H512NWxxAM CMP locking support
  mtd: spi-nor: Add steps for testing locking with CMP
  mtd: spi-nor: swp: Add support for the complement feature
  mtd: spi-nor: Add steps for testing locking support
  mtd: maps: remove obsolete impa7 map driver
  mtd: maps: remove uclinux map driver
  mtd: maps: remove AMD Élan specific drivers
  mtd: inftlmount: convert printk(KERN_WARNING) to pr_warn
  mtd: Consistently define pci_device_ids
  ...

3 files changed, 29 insertions, 3 deletions

diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
index e8201d1b7cf9..006ca8c978a9 100644
--- a/include/linux/mtd/nand-qpic-common.h
+++ b/include/linux/mtd/nand-qpic-common.h
@@ -9,6 +9,8 @@
 #ifndef __MTD_NAND_QPIC_COMMON_H__
 #define __MTD_NAND_QPIC_COMMON_H__
 
+#include <linux/mtd/rawnand.h>
+
 /* NANDc reg offsets */
 #define	NAND_FLASH_CMD			0x00
 #define	NAND_ADDR0			0x04
@@ -394,7 +396,7 @@ struct qcom_nand_controller {
 
 	const struct qcom_nandc_props *props;
 
-	struct nand_controller *controller;
+	struct nand_controller controller;
 	struct qpic_spi_nand *qspi;
 	struct list_head host_list;
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index cdcfe0fd2e7d..4b92494827b1 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -21,8 +21,8 @@
 /* Flash opcodes. */
 #define SPINOR_OP_WRDI		0x04	/* Write disable */
 #define SPINOR_OP_WREN		0x06	/* Write enable */
-#define SPINOR_OP_RDSR		0x05	/* Read status register */
-#define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
+#define SPINOR_OP_RDSR		0x05	/* Read status register 1 */
+#define SPINOR_OP_WRSR		0x01	/* Write status register 1 */
 #define SPINOR_OP_RDSR2		0x3f	/* Read status register 2 */
 #define SPINOR_OP_WRSR2		0x3e	/* Write status register 2 */
 #define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
@@ -125,6 +125,7 @@
 #define SR2_LB1			BIT(3)	/* Security Register Lock Bit 1 */
 #define SR2_LB2			BIT(4)	/* Security Register Lock Bit 2 */
 #define SR2_LB3			BIT(5)	/* Security Register Lock Bit 3 */
+#define SR2_CMP_BIT6		BIT(6)
 #define SR2_QUAD_EN_BIT7	BIT(7)
 
 /* Supported SPI protocols */
@@ -371,6 +372,7 @@ struct spi_nor_flash_parameter;
  * @reg_proto:		the SPI protocol for read_reg/write_reg/erase operations
  * @sfdp:		the SFDP data of the flash
  * @debugfs_root:	pointer to the debugfs directory
+ * @dfs_sr_cache:	Status Register cached value for debugfs use only
  * @controller_ops:	SPI NOR controller driver specific operations.
  * @params:		[FLASH-SPECIFIC] SPI NOR flash parameters and settings.
  *                      The structure includes legacy flash parameters and
@@ -409,6 +411,7 @@ struct spi_nor {
 	enum spi_nor_cmd_ext	cmd_ext_type;
 	struct sfdp		*sfdp;
 	struct dentry		*debugfs_root;
+	u8			dfs_sr_cache[2];
 
 	const struct spi_nor_controller_ops *controller_ops;
 
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index f53f5f0499b4..ec6efcfeef83 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -583,6 +583,7 @@ enum spinand_bus_interface {
  * @op_variants.read_cache: variants of the read-cache operation
  * @op_variants.write_cache: variants of the write-cache operation
  * @op_variants.update_cache: variants of the update-cache operation
+ * @op_variants.cont_read_cache: variants of the continuous read-cache operation
  * @vendor_ops: vendor specific operations
  * @select_target: function used to select a target/die. Required only for
  *		   multi-die chips
@@ -592,6 +593,7 @@ enum spinand_bus_interface {
  * @user_otp: SPI NAND user OTP info.
  * @read_retries: the number of read retry modes supported
  * @set_read_retry: enable/disable read retry for data recovery
+ * @set_randomizer: enable/disable randomizer support
  *
  * Each SPI NAND manufacturer driver should have a spinand_info table
  * describing all the chips supported by the driver.
@@ -607,6 +609,7 @@ struct spinand_info {
 		const struct spinand_op_variants *read_cache;
 		const struct spinand_op_variants *write_cache;
 		const struct spinand_op_variants *update_cache;
+		const struct spinand_op_variants *cont_read_cache;
 	} op_variants;
 	const struct spinand_op_variants *vendor_ops;
 	int (*select_target)(struct spinand_device *spinand,
@@ -620,6 +623,8 @@ struct spinand_info {
 	unsigned int read_retries;
 	int (*set_read_retry)(struct spinand_device *spinand,
 			     unsigned int read_retry);
+	int (*set_randomizer)(struct spinand_device *spinand,
+			      bool enable);
 };
 
 #define SPINAND_ID(__method, ...)					\
@@ -636,6 +641,14 @@ struct spinand_info {
 		.update_cache = __update,				\
 	}
 
+#define SPINAND_INFO_OP_VARIANTS_WITH_CONT(__read, __write, __update, __cont_read) \
+	{								\
+		.read_cache = __read,					\
+		.write_cache = __write,					\
+		.update_cache = __update,				\
+		.cont_read_cache = __cont_read,				\
+	}
+
 #define SPINAND_INFO_VENDOR_OPS(__ops)					\
 	.vendor_ops = __ops
 
@@ -676,6 +689,9 @@ struct spinand_info {
 	.read_retries = __read_retries,					\
 	.set_read_retry = __set_read_retry
 
+#define SPINAND_RANDOMIZER(__set_randomizer)				\
+	.set_randomizer = __set_randomizer
+
 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants,	\
 		     __flags, ...)					\
 	{								\
@@ -707,6 +723,7 @@ struct spinand_dirmap {
  * @read_cache: read cache op template
  * @write_cache: write cache op template
  * @update_cache: update cache op template
+ * @cont_read_cache: continuous read cache op template (optional)
  */
 struct spinand_mem_ops {
 	struct spi_mem_op reset;
@@ -721,6 +738,7 @@ struct spinand_mem_ops {
 	const struct spi_mem_op *read_cache;
 	const struct spi_mem_op *write_cache;
 	const struct spi_mem_op *update_cache;
+	const struct spi_mem_op *cont_read_cache;
 };
 
 /**
@@ -759,6 +777,7 @@ struct spinand_mem_ops {
  * @user_otp: SPI NAND user OTP info.
  * @read_retries: the number of read retry modes supported
  * @set_read_retry: Enable/disable the read retry feature
+ * @set_randomizer: Enable/disable the randomizer feature
  */
 struct spinand_device {
 	struct nand_device base;
@@ -792,6 +811,8 @@ struct spinand_device {
 	bool cont_read_possible;
 	int (*set_cont_read)(struct spinand_device *spinand,
 			     bool enable);
+	int (*set_randomizer)(struct spinand_device *spinand,
+			      bool enable);
 
 	const struct spinand_fact_otp *fact_otp;
 	const struct spinand_user_otp *user_otp;