Merge tag 'edac_updates_for_v7.2_rc1' of gitolite.kernel.org:pub/scm/linux/kernel/git/ras/ras

Pull EDAC updates from Borislav Petkov:

 - Fix a malformed Kconfig default for the AMD Address Translation
   Library

 - Make sure i10nm loads successfully when the ADXL address decoder is
   absent because former has decoding capabilities too

 - Ensure error reporting is cleanly disabled on driver teardown and on
   failed initialization for several legacy Intel EDAC drivers

 - Fix a grammar issue in a diagnostic warning in the Sandy Bridge
   driver

 - Fix a missing resource release callback and incorrect memory topology
   parsing in the igen6 driver, and add support for Intel Panther Lake-H
   and Nova Lake-H SoCs

 - Fix an out-of-bounds shift causing undefined behaviour in the Skylake
   driver

 - Consolidate memory controller register access helpers into shared
   common code across the Intel Skylake, Ice Lake, and Meteor Lake
   drivers

 - Introduce sub-channel awareness and Rank Retry Logic improvements to
   the Intel Skylake and i10nm drivers in preparation for Diamond Rapids
   server support

 - Add Rank Retry Logic support for Intel Diamond Rapids server to
   imh_edac

 - Make In-Band ECC detection registers configurable per SoC in the
   igen6 driver

 - Standardize PCI device ID table definitions across all EDAC drivers
   to use named field initializers and standard PCI helper macros

* tag 'edac_updates_for_v7.2_rc1' of gitolite.kernel.org:pub/scm/linux/kernel/git/ras/ras: (22 commits)
  EDAC: Consistently define pci_device_ids using named initializers
  EDAC/igen6: Add Intel Nova Lake-H SoC support
  EDAC/igen6: Make registers for detecting IBECC configurable
  EDAC/imh: Add RRL support for Intel Diamond Rapids server
  EDAC/{skx_common,i10nm}: Prepare RRL for sub-channel granularity
  EDAC/skx_common: Add SubChannel support to ADXL decode
  EDAC/{skx_common,i10nm}: Move RRL handling to common code
  EDAC/{skx_common,i10nm}: Introduce rrl_ctrl_mode
  EDAC/{skx_common,i10nm}: Rename rrl_mode to rrl_source_type
  EDAC/{skx_common,skx,i10nm}: Split skx_set_decode()
  EDAC/{skx_common,i10nm,imh}: Move MC register access helpers to skx_common
  EDAC/{skx_common,skx}: Fix UBSAN shift-out-of-bounds in skx_get_dimm_info
  EDAC/igen6: Add one Intel Panther Lake-H SoC support
  EDAC/igen6: Fix memory topology parsing for Panther Lake-H SoCs
  EDAC/igen6: Fix call trace due to missing release()
  EDAC/sb_edac: fix grammar in sb_decode_ddr3 warning
  EDAC/i5400: disable error reporting at teardown and refactor helper
  EDAC/i5100: disable error reporting at teardown and create helper
  EDAC/i5000: disable error reporting at teardown and refactor helper
  EDAC/i7300: disable error reporting if init fails and refactor helper
  ...

1 files changed, 3 insertions, 0 deletions

diff --git a/include/linux/edac.h b/include/linux/edac.h
index deba46b3ee25..e6b4e51130e5 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -184,6 +184,7 @@ static inline char *mc_event_error_type(const unsigned int err_type)
  * @MEM_DDR5:		Unbuffered DDR5 RAM
  * @MEM_RDDR5:		Registered DDR5 RAM
  * @MEM_LRDDR5:		Load-Reduced DDR5 memory.
+ * @MEM_LPDDR5:		Low-Power DDR5 memory.
  * @MEM_NVDIMM:		Non-volatile RAM
  * @MEM_WIO2:		Wide I/O 2.
  * @MEM_HBM2:		High bandwidth Memory Gen 2.
@@ -216,6 +217,7 @@ enum mem_type {
 	MEM_DDR5,
 	MEM_RDDR5,
 	MEM_LRDDR5,
+	MEM_LPDDR5,
 	MEM_NVDIMM,
 	MEM_WIO2,
 	MEM_HBM2,
@@ -247,6 +249,7 @@ enum mem_type {
 #define MEM_FLAG_DDR5		BIT(MEM_DDR5)
 #define MEM_FLAG_RDDR5		BIT(MEM_RDDR5)
 #define MEM_FLAG_LRDDR5		BIT(MEM_LRDDR5)
+#define MEM_FLAG_LPDDR5		BIT(MEM_LPDDR5)
 #define MEM_FLAG_NVDIMM		BIT(MEM_NVDIMM)
 #define MEM_FLAG_WIO2		BIT(MEM_WIO2)
 #define MEM_FLAG_HBM2		BIT(MEM_HBM2)