diff options
| author | Jiannan Du <shatyuka@qq.com> | 2026-10-14 22:37:23 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-10-14 17:40:30 +0200 |
| commit | 1184f87e2790e8af9be3116f608d2e86b4792d7d (patch) | |
| tree | b5282cbabf6eb1696007314a9a4347a68ebf5a6f /drivers/tty | |
| parent | 9105207b0287b5024bd53041ab1f700e152289c6 (diff) | |
tty: hvc: dcc: Detect JTAG connection only on CPU core 0
On SMP, migration can occur inside hvc_dcc_check() during device_initcall,
so the CPU writing the probe character and the CPU reading the TXfull
status may not be the same, which can hang the system.
Commit 4419da5d5d4b1788568b ("tty: hvc: dcc: Bind driver to CPU core0
for reads and writes") cached the DCC availability detected on core 0
during console_initcall. However, this is not sufficient: if core 0
does not detect DCC as available and another CPU later calls
hvc_dcc_check(), the check is not actually performed on core 0.
Since JTAG is not expected to be plugged or unplugged during kernel
boot, especially between console_initcall and device_initcall, checking
DCC availability multiple times is unnecessary. Cache the return value
from hvc_dcc_console_init and reuse it in hvc_dcc_init. This avoids
complex SMP-related code and ensures the result is always from core 0.
Signed-off-by: Jiannan Du <shatyuka@qq.com>
Link: https://patch.msgid.link/tencent_77968AD30F111278CBAE934BCFD0AF00E807@qq.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/hvc/hvc_dcc.c | 30 |
1 files changed, 8 insertions, 22 deletions
diff --git a/drivers/tty/hvc/hvc_dcc.c b/drivers/tty/hvc/hvc_dcc.c index dfc5c9c38f07..0223b26b5b28 100644 --- a/drivers/tty/hvc/hvc_dcc.c +++ b/drivers/tty/hvc/hvc_dcc.c @@ -29,6 +29,9 @@ static DEFINE_SPINLOCK(dcc_lock); static DEFINE_KFIFO(inbuf, u8, DCC_INBUF_SIZE); static DEFINE_KFIFO(outbuf, u8, DCC_OUTBUF_SIZE); +/* Cached result of hvc_dcc_check() on core 0 */ +static bool dcc_core0_available; + static void dcc_uart_console_putchar(struct uart_port *port, u8 ch) { while (__dcc_getstatus() & DCC_STATUS_TX) @@ -90,36 +93,18 @@ static ssize_t hvc_dcc_get_chars(uint32_t vt, u8 *buf, size_t count) } /* - * Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled, - * then we assume then this function will be called first on core0. That way, - * dcc_core0_available will be true only if it's available on core0. + * Check if the DCC is enabled. This function will be called once on core 0. */ static bool hvc_dcc_check(void) { unsigned long time = jiffies + (HZ / 10); - static bool dcc_core0_available; - - /* - * If we're not on core 0, but we previously confirmed that DCC is - * active, then just return true. - */ - int cpu = get_cpu(); - - if (IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP) && cpu && dcc_core0_available) { - put_cpu(); - return true; - } - - put_cpu(); /* Write a test character to check if it is handled */ __dcc_putchar('\n'); while (time_is_after_jiffies(time)) { - if (!(__dcc_getstatus() & DCC_STATUS_TX)) { - dcc_core0_available = true; + if (!(__dcc_getstatus() & DCC_STATUS_TX)) return true; - } } return false; @@ -265,7 +250,8 @@ static int __init hvc_dcc_console_init(void) { int ret; - if (!hvc_dcc_check()) + dcc_core0_available = hvc_dcc_check(); + if (!dcc_core0_available) return -ENODEV; /* Returns -1 if error */ @@ -279,7 +265,7 @@ static int __init hvc_dcc_init(void) { struct hvc_struct *p; - if (!hvc_dcc_check()) + if (!dcc_core0_available) return -ENODEV; if (IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP)) { |