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authorSven Schnelle <svens@linux.ibm.com>2025-01-08 15:27:04 +0100
committerAlexander Gordeev <agordeev@linux.ibm.com>2025-01-13 09:50:18 +0100
commit94446b4dcbbee79ff18173435950b2d1a7513c1b (patch)
treef96080a62aee8758e56a7ca7d8c3d04537e8eb58 /arch/s390
parent90c5515dcb9c824db244f42a98c765bd0542f109 (diff)
s390/ebcdic: Use exrl instead of ex
exrl is present in all machines currently supported, therefore prefer it over ex. This saves one instruction and doesn't need an additional register to hold the address of the target instruction. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
Diffstat (limited to 'arch/s390')
-rw-r--r--arch/s390/include/asm/ebcdic.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/s390/include/asm/ebcdic.h b/arch/s390/include/asm/ebcdic.h
index efb50fc6866c..cfa340552328 100644
--- a/arch/s390/include/asm/ebcdic.h
+++ b/arch/s390/include/asm/ebcdic.h
@@ -25,15 +25,15 @@ codepage_convert(const __u8 *codepage, volatile char *addr, unsigned long nr)
if (nr-- <= 0)
return;
asm volatile(
- " bras 1,1f\n"
- " tr 0(1,%0),0(%2)\n"
- "0: tr 0(256,%0),0(%2)\n"
+ " j 2f\n"
+ "0: tr 0(1,%0),0(%2)\n"
+ "1: tr 0(256,%0),0(%2)\n"
" la %0,256(%0)\n"
- "1: ahi %1,-256\n"
- " jnm 0b\n"
- " ex %1,0(1)"
+ "2: ahi %1,-256\n"
+ " jnm 1b\n"
+ " exrl %1,0b"
: "+&a" (addr), "+&a" (nr)
- : "a" (codepage) : "cc", "memory", "1");
+ : "a" (codepage) : "cc", "memory");
}
#define ASCEBC(addr,nr) codepage_convert(_ascebc, addr, nr)