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authorInochi Amaoto <inochiama@gmail.com>2025-06-09 07:28:25 +0800
committerInochi Amaoto <inochiama@gmail.com>2025-07-23 09:55:13 +0800
commit95f119e36443b0028d78986f01f382024c811ddb (patch)
tree0adbe9144d8a4259cd49287ba97684c95e275fa6 /arch/riscv
parent616c84f0473b1292a232b979c5a441de3039bb88 (diff)
riscv: dts: sophgo: sg2044: Add system controller device
The TOP system controller device is necessary for the SG2044 clock controller. Add it to the SoC device tree. Link: https://lore.kernel.org/r/20250608232836.784737-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/boot/dts/sophgo/sg2044.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index d67e45f77d6e..a0c13d8d26af 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -76,6 +76,13 @@
status = "disabled";
};
+ syscon: syscon@7050000000 {
+ compatible = "sophgo,sg2044-top-syscon", "syscon";
+ reg = <0x70 0x50000000 0x0 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+
rst: reset-controller@7050003000 {
compatible = "sophgo,sg2044-reset",
"sophgo,sg2042-reset";