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authorMarek Vasut <marek.vasut+renesas@mailbox.org>2025-08-06 17:04:27 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-08-12 09:38:53 +0200
commit256feb5be482315a91c1bd1a1808276f57ef76dd (patch)
tree1d887268e161c661eddb6f3141837f349dea9e27 /arch/arm/boot
parent95319aaa3ffc680cab9abe6e7197299561e890de (diff)
ARM: dts: renesas: r7s72100: Add boot phase tags
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas RZ/A1 SoCs. All SoCs require BSC bus, PFC pin control, and OSTM0 timer access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains the PFC and OSTM IPs. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806150448.9669-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/renesas/r7s72100-genmai.dts4
-rw-r--r--arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts4
-rw-r--r--arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts3
-rw-r--r--arch/arm/boot/dts/renesas/r7s72100.dtsi3
4 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
index c81840dfb7da..3c3756509714 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
@@ -203,6 +203,7 @@
};
&ostm0 {
+ bootph-all;
status = "okay";
};
@@ -258,6 +259,7 @@
};
scif2_pins: serial2 {
+ bootph-all;
/* P3_0 as TxD2; P3_2 as RxD2 */
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
@@ -286,7 +288,7 @@
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
-
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
index 9d29861f23f1..23ddec217685 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
@@ -59,6 +59,7 @@
&pinctrl {
scif2_pins: serial2 {
+ bootph-all;
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
@@ -99,6 +100,7 @@
};
&ostm0 {
+ bootph-all;
status = "okay";
};
@@ -109,7 +111,7 @@
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
-
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
index 25c6d0c78828..91178fb9e721 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
@@ -199,6 +199,7 @@
/* Serial Console */
scif2_pins: serial2 {
+ bootph-all;
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
};
@@ -264,6 +265,7 @@
};
&ostm0 {
+ bootph-all;
status = "okay";
};
@@ -278,6 +280,7 @@
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi
index 1a866dbaf5e9..a1e4e9ac8f62 100644
--- a/arch/arm/boot/dts/renesas/r7s72100.dtsi
+++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi
@@ -41,6 +41,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x18000000>;
+ bootph-all;
};
cpus {
@@ -107,6 +108,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ bootph-all;
L2: cache-controller@3ffff000 {
compatible = "arm,pl310-cache";
@@ -557,6 +559,7 @@
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
+ bootph-all;
reg = <0xfcfe3000 0x4230>;