diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-06-18 15:03:21 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-06-18 15:03:21 -0700 |
| commit | 53c7db5c1916afcecc8683ae01ff8415c708a883 (patch) | |
| tree | b22102348a7a17d1e33a680587f060d79d3322cc /Documentation/devicetree | |
| parent | 7c6742507c58cfdf2fa695ac895a33564b6aa252 (diff) | |
| parent | 8b2c4f88c6ee86efdbc81bed1684e13e2efebd53 (diff) | |
Merge tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Add new generic callbacks to populate per-pin pin controllers
creating groups and functions from the device tree building out
pinctrl_generic_to_map() and move the Spacemit driver over to use
this
- Generic board-level pin control driver using the mux framework
New pin controller drivers:
- Amlogic (meson) A9 SoC
- Aspeed AST2700 SoC0 and SoC1
- nVidia Tegra264 and Tegra238
- Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM
- Renesas RZ/G3L SoC
- UltraRISC DP1000
Improvements:
- Handle pull up/pull down properly in the Renesas RZG2L driver
- Fix up nVidia Tegra 234 DT bindings
- Fix up pin definitions in the Qualcomm Eliza driver
- Qualcomm PM8010 GPIO support in the PM8010
- Qualcomm SM6115 EGPIO support in the SM6115
- Switch Qualcomm LPASS LPI drivers to use runtime PM for power
management
- Clean up the Qualcomm Kconfig business a bit to include the
necessary drivers for each subarch
- Fix output glitch in the Amlogic (meson) A4 pin controller
- Move the Airoha driver from the Mediatek directory to its own
directory. It is too different from other Mediatek hardware
- A slew of fixes to the Airoha AN7581 and AN7583 drivers"
* tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits)
pinctrl: Export pinctrl_get_group_selector()
pinctrl: Match DT helper types
pinctrl: qcom: Register functions before enabling pinctrl
pinctrl: meson: amlogic-a4: use nolock get range
pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver
dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller
pinctrl: qcom: Remove unused macro definitions
pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA
pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA
pinctrl: tegra238: add missing AON pin groups
dt-bindings: pinctrl: tegra238: add missing AON pin groups
pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function
pinctrl: airoha: an7583: fix phy1_led1 pin function
pinctrl: airoha: an7583: add missed gpio22 pin group
pinctrl: airoha: an7583: fix gpio21 pin group
pinctrl: airoha: fix pwm pin function for an7581 and an7583
pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function
pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function
pinctrl: airoha: an7583: fix misprint in gpio19 pinconf
pinctrl: airoha: an7581: fix misprint in gpio19 pinconf
...
Diffstat (limited to 'Documentation/devicetree')
29 files changed, 2500 insertions, 28 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml index 154e03da8ce9..f87b8274cc37 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -34,7 +34,7 @@ properties: interrupts: minItems: 2 - maxItems: 10 + maxItems: 11 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -61,7 +61,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 - maxItems: 10 + maxItems: 11 patternProperties: # It's pretty scary, but the basic idea is that: @@ -130,8 +130,8 @@ allOf: then: properties: interrupts: - minItems: 10 - maxItems: 10 + minItems: 11 + maxItems: 11 - if: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 6ba66c2033b4..b69db1b95345 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-a9 - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml new file mode 100644 index 000000000000..407a64f28d49 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC0 Pin Controller + +maintainers: + - Billy Tsai <billy_tsai@aspeedtech.com> + +description: > + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC0. + + The SoC0 pin controller manages pin functions including eMMC, VGA DDC, + dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces. + +properties: + compatible: + const: aspeed,ast2700-soc0-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If 'function' is present, the node describes a pinmux state and must + specify 'groups'. + + For pin configuration, exactly one of 'groups' or 'pins' must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + + additionalProperties: false + + properties: + function: + enum: + - EMMC + - JTAGDDR + - JTAGM0 + - JTAGPCIEA + - JTAGPCIEB + - JTAGPSP + - JTAGSSP + - JTAGTSP + - JTAGUSB3A + - JTAGUSB3B + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2AD0 + - USB2AD1 + - USB2AH + - USB2AHP + - USB2AHPD0 + - USB2AXH + - USB2AXH2B + - USB2AXHD1 + - USB2AXHP + - USB2AXHP2B + - USB2AXHPD1 + - USB2BD0 + - USB2BD1 + - USB2BH + - USB2BHP + - USB2BHPD0 + - USB2BXH + - USB2BXH2A + - USB2BXHD1 + - USB2BXHP + - USB2BXHP2A + - USB2BXHPD1 + - USB3AXH + - USB3AXH2B + - USB3AXHD + - USB3AXHP + - USB3AXHP2B + - USB3AXHPD + - USB3BXH + - USB3BXH2A + - USB3BXHD + - USB3BXHP + - USB3BXHP2A + - USB3BXHPD + - VB + - VGADDC + + groups: + enum: + - EMMCCDN + - EMMCG1 + - EMMCG4 + - EMMCG8 + - EMMCWPN + - JTAG0 + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2A + - USB2AAP + - USB2ABP + - USB2ADAP + - USB2AH + - USB2AHAP + - USB2B + - USB2BAP + - USB2BBP + - USB2BDBP + - USB2BH + - USB2BHBP + - USB3A + - USB3AAP + - USB3ABP + - USB3B + - USB3BAP + - USB3BBP + - VB0 + - VB1 + - VGADDC + + pins: + enum: + - AB13 + - AB14 + - AC13 + - AC14 + - AD13 + - AD14 + - AE13 + - AE14 + - AE15 + - AF13 + - AF14 + - AF15 + + drive-strength: + enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml new file mode 100644 index 000000000000..76944fd14e2c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml @@ -0,0 +1,760 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC1 Pin Controller + +maintainers: + - Billy Tsai <billy_tsai@aspeedtech.com> + +description: + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC1. + + The SoC1 pin controller manages pin functions including eSPI, LPC and I2C, + among others. + +properties: + compatible: + const: aspeed,ast2700-soc1-pinctrl + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If `function` is present, the node describes a pinmux state and must + specify `groups`. + + For pin configuration, exactly one of `groups` or `pins` must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + additionalProperties: false + + properties: + function: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C0 + - I3C1 + - I3C10 + - I3C11 + - I3C12 + - I3C13 + - I3C14 + - I3C15 + - I3C2 + - I3C3 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PCIERC + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2C + - USB2D + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + groups: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - DI2C0 + - DI2C1 + - DI2C10 + - DI2C11 + - DI2C12 + - DI2C13 + - DI2C14 + - DI2C15 + - DI2C2 + - DI2C3 + - DI2C8 + - DI2C9 + - DSGPM0 + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - HVI3C0 + - HVI3C1 + - HVI3C12 + - HVI3C13 + - HVI3C14 + - HVI3C15 + - HVI3C2 + - HVI3C3 + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C10 + - I3C11 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - LTPI_PS_I2C0 + - LTPI_PS_I2C1 + - LTPI_PS_I2C2 + - LTPI_PS_I2C3 + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PE2SGRSTN + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2CD + - USB2CH + - USB2CU + - USB2CUD + - USB2DD + - USB2DH + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + pins: + enum: + - A14 + - A15 + - A18 + - A19 + - A21 + - A22 + - A23 + - A24 + - A25 + - A26 + - A6 + - A7 + - A8 + - AA12 + - AA13 + - AA14 + - AA15 + - AA16 + - AA17 + - AA18 + - AA20 + - AA21 + - AA22 + - AA23 + - AA24 + - AA25 + - AA26 + - AB15 + - AB16 + - AB17 + - AB18 + - AB19 + - AB20 + - AB21 + - AB22 + - AB23 + - AB24 + - AB25 + - AB26 + - AC15 + - AC16 + - AC17 + - AC18 + - AC19 + - AC20 + - AC22 + - AC24 + - AC25 + - AC26 + - AD15 + - AD16 + - AD17 + - AD18 + - AD19 + - AD20 + - AD22 + - AD25 + - AD26 + - AE16 + - AE17 + - AE18 + - AE19 + - AE20 + - AE21 + - AE23 + - AE25 + - AE26 + - AF16 + - AF17 + - AF18 + - AF19 + - AF20 + - AF21 + - AF23 + - AF25 + - AF26 + - B10 + - B11 + - B12 + - B13 + - B14 + - B15 + - B16 + - B18 + - B19 + - B21 + - B22 + - B23 + - B24 + - B25 + - B26 + - B6 + - B7 + - B8 + - B9 + - C10 + - C11 + - C12 + - C13 + - C14 + - C15 + - C16 + - C17 + - C18 + - C19 + - C20 + - C23 + - C26 + - C6 + - C7 + - C8 + - C9 + - D10 + - D12 + - D14 + - D15 + - D19 + - D20 + - D24 + - D26 + - D7 + - D8 + - D9 + - E10 + - E11 + - E12 + - E13 + - E14 + - E26 + - E7 + - E8 + - E9 + - F10 + - F11 + - F12 + - F13 + - F14 + - F26 + - F7 + - F8 + - F9 + - G10 + - G11 + - G7 + - G8 + - G9 + - H10 |
