Merge tag 'loongarch-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch updates from Huacai Chen:

 - Adjust build infrastructure for 32BIT/64BIT

 - Add HIGHMEM (PKMAP and FIX_KMAP) support

 - Show and handle CPU vulnerabilites correctly

 - Batch the icache maintenance for jump_label

 - Add more atomic instructions support for BPF JIT

 - Add more features (e.g. fsession) support for BPF trampoline

 - Some bug fixes and other small changes

* tag 'loongarch-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: (21 commits)
  selftests/bpf: Enable CAN_USE_LOAD_ACQ_STORE_REL for LoongArch
  LoongArch: BPF: Add fsession support for trampolines
  LoongArch: BPF: Introduce emit_store_stack_imm64() helper
  LoongArch: BPF: Support up to 12 function arguments for trampoline
  LoongArch: BPF: Support small struct arguments for trampoline
  LoongArch: BPF: Open code and remove invoke_bpf_mod_ret()
  LoongArch: BPF: Support load-acquire and store-release instructions
  LoongArch: BPF: Support 8 and 16 bit read-modify-write instructions
  LoongArch: BPF: Add the default case in emit_atomic() and rename it
  LoongArch: Define instruction formats for AM{SWAP/ADD}.{B/H} and DBAR
  LoongArch: Batch the icache maintenance for jump_label
  LoongArch: Add flush_icache_all()/local_flush_icache_all()
  LoongArch: Add spectre boundry for syscall dispatch table
  LoongArch: Show CPU vulnerabilites correctly
  LoongArch: Make arch_irq_work_has_interrupt() true only if IPI HW exist
  LoongArch: Use get_random_canary() for stack canary init
  LoongArch: Improve the logging of disabling KASLR
  LoongArch: Align FPU register state to 32 bytes
  LoongArch: Handle CONFIG_32BIT in syscall_get_arch()
  LoongArch: Add HIGHMEM (PKMAP and FIX_KMAP) support
  ...

39 files changed, 726 insertions, 201 deletions

diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index ac714d14133a..3b042dbb2c41 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -20,11 +20,11 @@ config LOONGARCH
 	select ARCH_HAS_FAST_MULTIPLIER
 	select ARCH_HAS_FORTIFY_SOURCE
 	select ARCH_HAS_KCOV
-	select ARCH_HAS_KERNEL_FPU_SUPPORT if CPU_HAS_FPU
+	select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && CPU_HAS_FPU
 	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
 	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
 	select ARCH_HAS_PREEMPT_LAZY
-	select ARCH_HAS_PTE_SPECIAL
+	select ARCH_HAS_PTE_SPECIAL if 64BIT
 	select ARCH_HAS_SET_MEMORY
 	select ARCH_HAS_SET_DIRECT_MAP
 	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
@@ -59,16 +59,15 @@ config LOONGARCH
 	select ARCH_KEEP_MEMBLOCK
 	select ARCH_MIGHT_HAVE_PC_PARPORT
 	select ARCH_MIGHT_HAVE_PC_SERIO
-	select ARCH_SPARSEMEM_ENABLE
 	select ARCH_STACKWALK
 	select ARCH_SUPPORTS_ACPI
 	select ARCH_SUPPORTS_ATOMIC_RMW
-	select ARCH_SUPPORTS_HUGETLBFS
+	select ARCH_SUPPORTS_HUGETLBFS if 64BIT
 	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
 	select ARCH_SUPPORTS_LTO_CLANG
 	select ARCH_SUPPORTS_LTO_CLANG_THIN
 	select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS
-	select ARCH_SUPPORTS_NUMA_BALANCING
+	select ARCH_SUPPORTS_NUMA_BALANCING if NUMA
 	select ARCH_SUPPORTS_PER_VMA_LOCK
 	select ARCH_SUPPORTS_RT
 	select ARCH_SUPPORTS_SCHED_SMT if SMP
@@ -78,10 +77,10 @@ config LOONGARCH
 	select ARCH_USE_MEMTEST
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_USE_QUEUED_SPINLOCKS
-	select ARCH_WANT_DEFAULT_BPF_JIT
+	select ARCH_WANT_DEFAULT_BPF_JIT if HAVE_EBPF_JIT
 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
 	select ARCH_WANT_LD_ORPHAN_WARN
-	select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
+	select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if 64BIT
 	select ARCH_WANTS_NO_INSTR
 	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
 	select BUILDTIME_TABLE_SORT
@@ -89,13 +88,14 @@ config LOONGARCH
 	select CPU_PM
 	select EDAC_SUPPORT
 	select EFI
+	select GENERIC_ATOMIC64 if 32BIT
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_CMOS_UPDATE
 	select GENERIC_CPU_AUTOPROBE
 	select GENERIC_CPU_DEVICES
 	select GENERIC_CPU_VULNERABILITIES
 	select GENERIC_ENTRY
-	select GENERIC_GETTIMEOFDAY
+	select GENERIC_GETTIMEOFDAY if 64BIT
 	select GENERIC_IOREMAP if !ARCH_IOREMAP
 	select GENERIC_IRQ_MATRIX_ALLOCATOR
 	select GENERIC_IRQ_MULTI_HANDLER
@@ -110,16 +110,16 @@ config LOONGARCH
 	select GENERIC_PCI_IOMAP
 	select GENERIC_SCHED_CLOCK
 	select GENERIC_SMP_IDLE_THREAD
-	select GENERIC_TIME_VSYSCALL
+	select GENERIC_TIME_VSYSCALL if GENERIC_GETTIMEOFDAY
 	select GPIOLIB
 	select HAS_IOPORT
-	select HAVE_ALIGNED_STRUCT_PAGE
+	select HAVE_ALIGNED_STRUCT_PAGE if 64BIT
 	select HAVE_ARCH_AUDITSYSCALL
-	select HAVE_ARCH_BITREVERSE
+	select HAVE_ARCH_BITREVERSE if 64BIT
 	select HAVE_ARCH_JUMP_LABEL
 	select HAVE_ARCH_JUMP_LABEL_RELATIVE
-	select HAVE_ARCH_KASAN
-	select HAVE_ARCH_KFENCE
+	select HAVE_ARCH_KASAN if 64BIT
+	select HAVE_ARCH_KFENCE if 64BIT
 	select HAVE_ARCH_KGDB if PERF_EVENTS
 	select HAVE_ARCH_KSTACK_ERASE
 	select HAVE_ARCH_MMAP_RND_BITS if MMU
@@ -127,8 +127,8 @@ config LOONGARCH
 	select HAVE_ARCH_SECCOMP
 	select HAVE_ARCH_SECCOMP_FILTER
 	select HAVE_ARCH_TRACEHOOK
-	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
-	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
+	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT
+	select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
 	select HAVE_ASM_MODVERSIONS
 	select HAVE_CMPXCHG_DOUBLE
 	select HAVE_CMPXCHG_LOCAL
@@ -142,7 +142,7 @@ config LOONGARCH
 	select HAVE_FTRACE_REGS_HAVING_PT_REGS
 	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS
 	select HAVE_DYNAMIC_FTRACE_WITH_REGS
-	select HAVE_EBPF_JIT
+	select HAVE_EBPF_JIT if 64BIT
 	select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN
 	select HAVE_EXIT_THREAD
 	select HAVE_GENERIC_TIF_BITS
@@ -165,9 +165,9 @@ config LOONGARCH
 	select HAVE_LIVEPATCH
 	select HAVE_MOD_ARCH_SPECIFIC
 	select HAVE_NMI
-	select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB
+	select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB && 64BIT
 	select HAVE_PCI
-	select HAVE_PERF_EVENTS
+	select HAVE_PERF_EVENTS if 64BIT
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
@@ -209,18 +209,50 @@ config LOONGARCH
 	select SYSCTL_ARCH_UNALIGN_ALLOW
 	select SYSCTL_ARCH_UNALIGN_NO_WARN
 	select SYSCTL_EXCEPTION_TRACE
-	select SWIOTLB
+	select SWIOTLB if 64BIT
 	select TRACE_IRQFLAGS_SUPPORT
 	select USE_PERCPU_NUMA_NODE_ID
 	select USER_STACKTRACE_SUPPORT
 	select VDSO_GETRANDOM
-	select ZONE_DMA32
+	select ZONE_DMA32 if 64BIT
+
+menu "Kernel type and options"
+
+choice
+	prompt "Kernel type"
 
 config 32BIT
-	bool
+	bool "32-bit kernel"
+	help
+	  Select this option if you want to build a 32-bit kernel.
 
 config 64BIT
-	def_bool y
+	bool "64-bit kernel"
+	help
+	  Select this option if you want to build a 64-bit kernel.
+
+endchoice
+
+if 32BIT
+
+choice
+	prompt "32-bit kernel sub-type"
+
+config 32BIT_REDUCED
+	bool "32-bit kernel for LA32R"
+	help
+	  Select this option if you want to build a 32-bit kernel for
+	  LoongArch32 Reduced (LA32R).
+
+config 32BIT_STANDARD
+	bool "32-bit kernel for LA32S"
+	help
+	  Select this option if you want to build a 32-bit kernel for
+	  LoongArch32 Standard (LA32S).
+
+endchoice
+
+endif
 
 config GENERIC_BUG
 	def_bool y
@@ -313,10 +345,13 @@ config RUSTC_HAS_ANNOTATE_TABLEJUMP
 	depends on RUST
 	def_bool $(rustc-option,-Cllvm-args=--loongarch-annotate-tablejump)
 
-menu "Kernel type and options"
-
 source "kernel/Kconfig.hz"
 
+config HIGHMEM
+	bool "High Memory Support"
+	depends on 32BIT
+	select KMAP_LOCAL
+
 choice
 	prompt "Page Table Layout"
 	default 16KB_2LEVEL if 32BIT
@@ -326,8 +361,17 @@ choice
 	  of page size and page table levels. The size of virtual memory
 	  address space are determined by the page table layout.
 
+config 4KB_2LEVEL
+	bool "4KB with 2 levels"
+	select HAVE_PAGE_SIZE_4KB
+	select PGTABLE_2LEVEL
+	help
+	  This option selects 4KB page size with 2 level page tables, which
+	  support a maximum of 32 bits of application virtual memory.
+
 config 4KB_3LEVEL
 	bool "4KB with 3 levels"
+	depends on 64BIT
 	select HAVE_PAGE_SIZE_4KB
 	select PGTABLE_3LEVEL
 	help
@@ -336,6 +380,7 @@ config 4KB_3LEVEL
 
 config 4KB_4LEVEL
 	bool "4KB with 4 levels"
+	depends on 64BIT
 	select HAVE_PAGE_SIZE_4KB
 	select PGTABLE_4LEVEL
 	help
@@ -352,6 +397,7 @@ config 16KB_2LEVEL
 
 config 16KB_3LEVEL
 	bool "16KB with 3 levels"
+	depends on 64BIT
 	select HAVE_PAGE_SIZE_16KB
 	select PGTABLE_3LEVEL
 	help
@@ -368,6 +414,7 @@ config 64KB_2LEVEL
 
 config 64KB_3LEVEL
 	bool "64KB with 3 levels"
+	depends on 64BIT
 	select HAVE_PAGE_SIZE_64KB
 	select PGTABLE_3LEVEL
 	help
@@ -465,6 +512,7 @@ config EFI_STUB
 
 config SMP
 	bool "Multi-Processing support"
+	depends on 64BIT
 	help
 	  This enables support for systems with more than one CPU. If you have
 	  a system with only one CPU, say N. If you have a system with more
@@ -503,6 +551,7 @@ config NR_CPUS
 config NUMA
 	bool "NUMA Support"
 	select SMP
+	depends on 64BIT
 	help
 	  Say Y to compile the kernel with NUMA (Non-Uniform Memory Access)
 	  support.  This option improves performance on systems with more
@@ -585,7 +634,7 @@ config CPU_HAS_FPU
 
 config CPU_HAS_LSX
 	bool "Support for the Loongson SIMD Extension"
-	depends on AS_HAS_LSX_EXTENSION
+	depends on AS_HAS_LSX_EXTENSION && 64BIT
 	help
 	  Loongson SIMD Extension (LSX) introduces 128 bit wide vector registers
 	  and a set of SIMD instructions to operate on them. When this option
@@ -600,7 +649,7 @@ config CPU_HAS_LSX
 config CPU_HAS_LASX
 	bool "Support for the Loongson Advanced SIMD Extension"
 	depends on CPU_HAS_LSX
-	depends on AS_HAS_LASX_EXTENSION
+	depends on AS_HAS_LASX_EXTENSION && 64BIT
 	help
 	  Loongson Advanced SIMD Extension (LASX) introduces 256 bit wide vector
 	  registers and a set of SIMD instructions to operate on them. When this
@@ -614,7 +663,7 @@ config CPU_HAS_LASX
 
 config CPU_HAS_LBT
 	bool "Support for the Loongson Binary Translation Extension"
-	depends on AS_HAS_LBT_EXTENSION
+	depends on AS_HAS_LBT_EXTENSION && 64BIT
 	help
 	  Loongson Binary Translation (LBT) introduces 4 scratch registers (SCR0
 	  to SCR3), x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop).
@@ -642,13 +691,13 @@ config ARCH_SELECTS_KEXEC_FILE
 	select HAVE_IMA_KEXEC if IMA
 
 config ARCH_SUPPORTS_CRASH_DUMP
-	def_bool y
+	def_bool 64BIT
 
 config ARCH_DEFAULT_CRASH_DUMP
-	def_bool y
+	def_bool 64BIT
 
 config ARCH_SELECTS_CRASH_DUMP
-	def_bool y
+	def_bool 64BIT
 	depends on CRASH_DUMP
 	select RELOCATABLE
 
@@ -657,6 +706,7 @@ config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
 
 config RELOCATABLE
 	bool "Relocatable kernel"
+	depends on 64BIT
 	select ARCH_HAS_RELR
 	help
 	  This builds the kernel as a Position Independent Executable (PIE),
@@ -693,7 +743,7 @@ source "kernel/livepatch/Kconfig"
 
 config PARAVIRT
 	bool "Enable paravirtualization code"
-	depends on AS_HAS_LVZ_EXTENSION
+	depends on AS_HAS_LVZ_EXTENSION && 64BIT
 	select HAVE_PV_STEAL_CLOCK_GEN
 	help
 	  This changes the kernel so it can modify itself when it is run
@@ -722,7 +772,7 @@ config ARCH_FLATMEM_ENABLE
 	depends on !NUMA
 
 config ARCH_SPARSEMEM_ENABLE
-	def_bool y
+	def_bool 64BIT
 	select SPARSEMEM_VMEMMAP_ENABLE
 	help
 	  Say Y to support efficient handling of sparse physical memory,
@@ -739,10 +789,12 @@ config MMU
 	default y
 
 config ARCH_MMAP_RND_BITS_MIN
-	default 12
+	default 10 if 32BIT
+	default 12 if 64BIT
 
 config ARCH_MMAP_RND_BITS_MAX
-	default 18
+	default 15 if 32BIT
+	default 20 if 64BIT
 
 config ARCH_SUPPORTS_UPROBES
 	def_bool y
diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile
index 8d45b860fe56..47516aeea9d2 100644
--- a/arch/loongarch/Makefile
+++ b/arch/loongarch/Makefile
@@ -25,6 +25,7 @@ endif
 #
 # Select the object file format to substitute into the linker script.
 #
+32bit-tool-archpref	= loongarch32
 64bit-tool-archpref	= loongarch64
 32bit-bfd		= elf32-loongarch
 64bit-bfd		= elf64-loongarch
@@ -51,7 +52,10 @@ KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
 CC_FLAGS_FTRACE := -fpatchable-function-entry=2
 endif
 
-ifdef CONFIG_64BIT
+ifdef CONFIG_32BIT
+tool-archpref		= $(32bit-tool-archpref)
+UTS_MACHINE		:= loongarch32
+else
 tool-archpref		= $(64bit-tool-archpref)
 UTS_MACHINE		:= loongarch64
 endif
@@ -62,9 +66,19 @@ ifneq ($(SUBARCH),$(ARCH))
   endif
 endif
 
+ifdef CONFIG_32BIT
+ifdef CONFIG_32BIT_STANDARD
+ld-emul			= $(32bit-emul)
+cflags-y		+= -march=la32v1.0 -mabi=ilp32s -mcmodel=normal
+else  # CONFIG_32BIT_REDUCED
+ld-emul			= $(32bit-emul)
+cflags-y		+= -march=la32rv1.0 -mabi=ilp32s -mcmodel=normal
+endif
+endif
+
 ifdef CONFIG_64BIT
 ld-emul			= $(64bit-emul)
-cflags-y		+= -mabi=lp64s -mcmodel=normal
+cflags-y		+= -march=loongarch64 -mabi=lp64s -mcmodel=normal
 endif
 
 cflags-y			+= -pipe $(CC_FLAGS_NO_FPU)
@@ -140,7 +154,12 @@ ifndef CONFIG_KASAN
 cflags-y += -fno-builtin-memcpy -fno-builtin-memmove -fno-builtin-memset
 endif
 
+ifdef CONFIG_32BIT
+load-y		= 0xa0200000
+else
 load-y		= 0x9000000000200000
+endif
+
 bootvars-y	= VMLINUX_LOAD_ADDRESS=$(load-y)
 
 drivers-$(CONFIG_PCI)		+= arch/loongarch/pci/
diff --git a/arch/loongarch/boot/Makefile b/arch/loongarch/boot/Makefile
index 4e1c374c5782..8b6d9b42b5f0 100644
--- a/arch/loongarch/boot/Makefile
+++ b/arch/loongarch/boot/Makefile
@@ -20,7 +20,13 @@ $(obj)/vmlinux.efi: vmlinux FORCE
 	$(call if_changed,objcopy)
 
 EFI_ZBOOT_PAYLOAD      := vmlinux.efi
+
+ifdef CONFIG_32BIT
+EFI_ZBOOT_BFD_TARGET   := elf32-loongarch
+EFI_ZBOOT_MACH_TYPE    := LOONGARCH32
+else
 EFI_ZBOOT_BFD_TARGET   := elf64-loongarch
 EFI_ZBOOT_MACH_TYPE    := LOONGARCH64
+endif
 
 include $(srctree)/drivers/firmware/efi/libstub/Makefile.zboot
diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/include/asm/cacheflush.h
index f8754d08a31a..190651be9546 100644
--- a/arch/loongarch/include/asm/cacheflush.h
+++ b/arch/loongarch/include/asm/cacheflush.h
@@ -32,8 +32,22 @@ static inline unsigned int cpu_last_level_cache_line_size(void)
 }
 
 asmlinkage void __flush_cache_all(void);
-void local_flush_icache_range(unsigned long start, unsigned long end);
 
+/*
+ * LoongArch maintains ICache/DCache coherency by hardware,
+ * we just need "ibar" to avoid instruction hazard here.
+ */
+static inline void local_flush_icache_all(void)
+{
+	asm volatile ("ibar\t0\n"::);
+}
+
+static inline void local_flush_icache_range(unsigned long start, unsigned long end)
+{
+	asm volatile ("ibar\t0\n"::);
+}
+
+#define flush_icache_all	local_flush_icache_all
 #define flush_icache_range	local_flush_icache_range
 #define flush_icache_user_range	local_flush_icache_range
 
diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h
index 8eefe7a2098b..62059c5551b9 100644
--- a/arch/loongarch/include/asm/cpu-features.h
+++ b/arch/loongarch/include/asm/cpu-features.h
@@ -35,6 +35,7 @@
  */
 #define cpu_has_cpucfg		cpu_opt(LOONGARCH_CPU_CPUCFG)
 #define cpu_has_lam		cpu_opt(LOONGARCH_CPU_LAM)
+#define cpu_has_lam_bh		cpu_opt(LOONGARCH_CPU_LAM_BH)
 #define cpu_has_scq		cpu_opt(LOONGARCH_CPU_SCQ)
 #define cpu_has_ual		cpu_opt(LOONGARCH_CPU_UAL)
 #define cpu_has_fpu		cpu_opt(LOONGARCH_CPU_FPU)
diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
index 1e60ab264cd0..91b96938861e 100644
--- a/arch/loongarch/include/asm/cpu.h
+++ b/arch/loongarch/include/asm/cpu.h
@@ -95,40 +95,42 @@ static inline char *id_to_core_name(unsigned int id)
  */
 #define CPU_FEATURE_CPUCFG		0	/* CPU has CPUCFG */
 #define CPU_FEATURE_LAM			1	/* CPU has Atomic instructions */
-#define CPU_FEATURE_SCQ			2	/* CPU has SC.Q instruction */
-#define CPU_FEATURE_UAL			3	/* CPU supports unaligned access */
-#define CPU_FEATURE_FPU			4	/* CPU has FPU */
-#define CPU_FEATURE_LSX			5	/* CPU has LSX (128-bit SIMD) */
-#define CPU_FEATURE_LASX		6	/* CPU has LASX (256-bit SIMD) */
-#define CPU_FEATURE_CRC32		7	/* CPU has CRC32 instructions */
-#define CPU_FEATURE_COMPLEX		8	/* CPU has Complex instructions */
-#define CPU_FEATURE_CRYPTO		9	/* CPU has Crypto instructions */
-#define CPU_FEATURE_LVZ			10	/* CPU has Virtualization extension */
-#define CPU_FEATURE_LBT_X86		11	/* CPU has X86 Binary Translation */
-#define CPU_FEATURE_LBT_ARM		12	/* CPU has ARM Binary Translation */
-#define CPU_FEATURE_LBT_MIPS		13	/* CPU has MIPS Binary Translation */
-#define CPU_FEATURE_TLB			14	/* CPU has TLB */
-#define CPU_FEATURE_CSR			15	/* CPU has CSR */
-#define CPU_FEATURE_IOCSR		16	/* CPU has IOCSR */
-#define CPU_FEATURE_WATCH		17	/* CPU has watchpoint registers */
-#define CPU_FEATURE_VINT		18	/* CPU has vectored interrupts */
-#define CPU_FEATURE_CSRIPI		19	/* CPU has CSR-IPI */
-#define CPU_FEATURE_EXTIOI		20	/* CPU has EXT-IOI */
-#define CPU_FEATURE_PREFETCH		21	/* CPU has prefetch instructions */
-#define CPU_FEATURE_PMP			22	/* CPU has perfermance counter */
-#define CPU_FEATURE_SCALEFREQ		23	/* CPU supports cpufreq scaling */
-#define CPU_FEATURE_FLATMODE		24	/* CPU has flat mode */
-#define CPU_FEATURE_EIODECODE		25	/* CPU has EXTIOI interrupt pin decode mode */
-#define CPU_FEATURE_GUESTID		26	/* CPU has GuestID feature */
-#define CPU_FEATURE_HYPERVISOR		27	/* CPU has hypervisor (running in VM) */
-#define CPU_FEATURE_PTW			28	/* CPU has hardware page table walker */
-#define CPU_FEATURE_LSPW		29	/* CPU has LSPW (lddir/ldpte instructions) */
-#define CPU_FEATURE_MSGINT		30	/* CPU has MSG interrupt */
-#define CPU_FEATURE_AVECINT		31	/* CPU has AVEC interrupt */
-#define CPU_FEATURE_REDIRECTINT		32	/* CPU has interrupt remapping */
+#define CPU_FEATURE_LAM_BH		2	/* CPU has AM{SWAP/ADD}[_DB].{B/H} instructions */
+#define CPU_FEATURE_SCQ			3	/* CPU has SC.Q instruction */
+#define CPU_FEATURE_UAL			4	/* CPU supports unaligned access */
+#define CPU_FEATURE_FPU			5	/* CPU has FPU */
+#define CPU_FEATURE_LSX			6	/* CPU has LSX (128-bit SIMD) */
+#define CPU_FEATURE_LASX		7	/* CPU has LASX (256-bit SIMD) */
+#define CPU_FEATURE_CRC32		8	/* CPU has CRC32 instructions */
+#define CPU_FEATURE_COMPLEX		9	/* CPU has Complex instructions */
+#define CPU_FEATURE_CRYPTO		10	/* CPU has Crypto instructions */
+#define CPU_FEATURE_LVZ			11	/* CPU has Virtualization extension */
+#define CPU_FEATURE_LBT_X86		12	/* CPU has X86 Binary Translation */
+#define CPU_FEATURE_LBT_ARM		13	/* CPU has ARM Binary Translation */
+#define CPU_FEATURE_LBT_MIPS		14	/* CPU has MIPS Binary Translation */
+#define CPU_FEATURE_TLB			15	/* CPU has TLB */
+#define CPU_FEATURE_CSR			16	/* CPU has CSR */
+#define CPU_FEATURE_IOCSR		17	/* CPU has IOCSR */
+#define CPU_FEATURE_WATCH		18	/* CPU has watchpoint registers */
+#define CPU_FEATURE_VINT		19	/* CPU has vectored interrupts */
+#define CPU_FEATURE_CSRIPI		20	/* CPU has CSR-IPI */
+#define CPU_FEATURE_EXTIOI		21	/* CPU has EXT-IOI */
+#define CPU_FEATURE_PREFETCH		22	/* CPU has prefetch instructions */
+#define CPU_FEATURE_PMP			23	/* CPU has perfermance counter */
+#define CPU_FEATURE_SCALEFREQ		24	/* CPU supports cpufreq scaling */
+#define CPU_FEATURE_FLATMODE		25	/* CPU has flat mode */
+#define CPU_FEATURE_EIODECODE		26	/* CPU has EXTIOI interrupt pin decode mode */
+#define CPU_FEATURE_GUESTID		27	/* CPU has GuestID feature */
+#define CPU_FEATURE_HYPERVISOR		28	/* CPU has hypervisor (running in VM) */
+#define CPU_FEATURE_PTW			29	/* CPU has hardware page table walker */
+#define CPU_FEATURE_LSPW		30	/* CPU has LSPW (lddir/ldpte instructions) */
+#define CPU_FEATURE_MSGINT		31	/* CPU has MSG interrupt */
+#define CPU_FEATURE_AVECINT		32	/* CPU has AVEC interrupt */
+#define CPU_FEATURE_REDIRECTINT		33	/* CPU has interrupt remapping */
 
 #define LOONGARCH_CPU_CPUCFG		BIT_ULL(CPU_FEATURE_CPUCFG)
 #define LOONGARCH_CPU_LAM		BIT_ULL(CPU_FEATURE_LAM)
+#define LOONGARCH_CPU_LAM_BH		BIT_ULL(CPU_FEATURE_LAM_BH)
 #define LOONGARCH_CPU_SCQ		BIT_ULL(CPU_FEATURE_SCQ)
 #define LOONGARCH_CPU_UAL		BIT_ULL(CPU_FEATURE_UAL)
 #define LOONGARCH_CPU_FPU		BIT_ULL(CPU_FEATURE_FPU)
diff --git a/arch/loongarch/include/asm/fixmap.h b/arch/loongarch/include/asm/fixmap.h
index d2e55ae55bb9..dce2da6ba787 100644
--- a/arch/loongarch/include/asm/fixmap.h
+++ b/arch/loongarch/include/asm/fixmap.h
@@ -8,10 +8,19 @@
 #ifndef _ASM_FIXMAP_H
 #define _ASM_FIXMAP_H
 
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_size.h>
+#endif
+
 #define NR_FIX_BTMAPS 64
 
 enum fixed_addresses {
 	FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+	FIX_KMAP_BEGIN,
+	FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_MAX_IDX * NR_CPUS) - 1,
+#endif
 	FIX_EARLYCON_MEM_BASE,
 	__end_of_fixed_addresses
 };
@@ -25,4 +34,9 @@ extern void __set_fixmap(enum fixed_addresses idx,
 
 #include <asm-generic/fixmap.h>
 
+/*
+ * Called from pagetable_init()
+ */
+extern void fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base);
+
 #endif
diff --git a/arch/loongarch/include/asm/highmem.h b/arch/loongarch/include/asm/highmem.h
new file mode 100644
index 000000000000..e6d7a662d340
--- /dev/null
+++ b/arch/loongarch/include/asm/highmem.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 2025 Loongson Technology Corporation Limited
+ */
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <asm/kmap_size.h>
+
+#ifndef __ASSEMBLER__
+
+extern pte_t *pkmap_page_table;
+
+#define ARCH_HAS_KMAP_FLUSH_TLB
+void kmap_flush_tlb(unsigned long addr);
+
+#endif /* !__ASSEMBLER__ */
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define LAST_PKMAP 1024
+#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
+#define PKMAP_NR(virt)	((virt - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)	(PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define flush_cache_kmaps() do {} while (0)
+
+#define arch_kmap_local_post_map(vaddr, pteval)	local_flush_tlb_one(vaddr)
+#define arch_kmap_local_post_unmap(vaddr)	local_flush_tlb_one(vaddr)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm/inst.h
index f9f207082d0e..76b723590023 100644
--- a/arch/loongarch/include/asm/inst.h
+++ b/arch/loongarch/include/asm/inst.h
@@ -36,6 +36,7 @@
 
 enum reg0i15_op {
 	break_op	= 0x54,
+	dbar_op		= 0x70e4,
 };
 
 enum reg0i26_op {
@@ -194,6 +195,10 @@ enum reg3_op {
 	fstxs_op	= 0x7070,
 	fstxd_op	= 0x7078,
 	scq_op		= 0x70ae,
+	amswapb_op	= 0x70b8,
+	amswaph_op	= 0x70b9,
+	amaddb_op	= 0x70ba,
+	amaddh_op	= 0x70bb,
 	amswapw_op	= 0x70c0,
 	amswapd_op	= 0x70c1,
 	amaddw_op	= 0x70c2,
@@ -543,6 +548,7 @@ static inline void emit_##NAME(union loongarch_instruction *insn,	\
 }
 
 DEF_EMIT_REG0I15_FORMAT(break, break_op)
+DEF_EMIT_REG0I15_FORMAT(dbar, dbar_op)
 
 /* like emit_break(imm) but returns a constant expression */
 #define __emit_break(imm)	((u32)((imm) | (break_op << 15)))
@@ -763,6 +769,8 @@ DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
 DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
 DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
 DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
+DEF_EMIT_REG3_FORMAT(amaddb, amaddb_op)
+DEF_EMIT_REG3_FORMAT(amaddh, amaddh_op)
 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
 DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
@@ -771,6 +779,8 @@ DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
 DEF_EMIT_REG3_FORMAT(amord, amord_op)
 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
 DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
+DEF_EMIT_REG3_FORMAT(amswapb, amswapb_op)
+DEF_EMIT_REG3_FORMAT(amswaph, amswaph_op)
 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
 
diff --git a/arch/loongarch/include/asm/irq_work.h b/arch/loongarch/include/asm/irq_work.h
index d63076e9160d..63aee0335d1a 100644
--- a/arch/loongarch/include/asm/irq_work.h
+++ b/arch/loongarch/include/asm/irq_work.h
@@ -4,7 +4,7 @@
 
 static inline bool arch_irq_work_has_interrupt(void)
 {
-	return IS_ENABLED(CONFIG_SMP);
+	return IS_ENABLED(CONFIG_SMP) && cpu_opt(LOONGARCH_CPU_CSRIPI);
 }
 
 #endif /* _ASM_LOONGARCH_IRQ_WORK_H */
diff --git a/arch/loongarch/include/asm/jump_label.h b/arch/loongarch/include/asm/jump_label.h
index dcaecf69ea5a..7ef4ae3abf08 100644
--- a/arch/loongarch/include/asm/jump_label.h
+++ b/arch/loongarch/include/asm/jump_label.h
@@ -13,6 +13,8 @@
 #include <linux/stringify.h>
 #include <asm/asm.h>
 
+#define HAVE_JUMP_LABEL_BATCH
+
 #define JUMP_LABEL_NOP_SIZE	4
 
 #ifdef CONFIG_32BIT
diff --git a/arch/loongarch/include/asm/page.h b/arch/loongarch/include/asm/page.h
index 79235f4fc399..b9d61f7c032c 100644
--- a/arch/loongarch/include/asm/page.h
+++ b/