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authorDave Airlie <airlied@redhat.com>2017-06-20 11:10:49 +1000
committerDave Airlie <airlied@redhat.com>2017-06-20 11:10:49 +1000
commitd02b0ffb005469ef4ee73610fb08dff45e4487f8 (patch)
tree3acf65e7109cbbde522ec0d9fa5cfc6064a8428c
parent4a525bad68b424d167042342db19d0c0e80e8b29 (diff)
parent7df1bb87b8cb0b618e4b5964f89d81d8ce52c58e (diff)
Merge branch 'linux-4.13' of git://github.com/skeggsb/linux into drm-next
- HDMI stereoscopic support - Rework of display code to properly support SOR pad macro routing on >=GM20x GPUs - Various other fixes/improvements. * 'linux-4.13' of git://github.com/skeggsb/linux: (73 commits) drm/nouveau/disp/nv50-: avoid creating ORs that aren't present on HW drm/nouveau: use proper prototype in nouveau_pmops_runtime() definition drm/nouveau: Skip vga_fini on non-PCI device drm/nouveau/tegra: Don't leave GPU in reset drm/nouveau/tegra: Skip manual unpowergating when not necessary drm/nouveau/hwmon: Change permissions to numeric drm/nouveau/hwmon: expose the auto_point and pwm_min/max attrs drm/nouveau/hwmon: Remove old code, add .write/.read operations drm/nouveau/hwmon: Add nouveau_hwmon_ops structure with .is_visible/.read_string drm/nouveau/hwmon: Add config for all sensors and their settings drm/nouveau/disp/gm200-: allow non-identity mapping of SOR <-> macro links drm/nouveau/disp/nv50-: implement a common supervisor 3.0 drm/nouveau/disp/nv50-: implement a common supervisor 2.2 drm/nouveau/disp/nv50-: implement a common supervisor 2.1 drm/nouveau/disp/nv50-: implement a common supervisor 2.0 drm/nouveau/disp/nv50-: implement a common supervisor 1.0 drm/nouveau/disp/nv50-gt21x: remove workaround for dp->tmds hotplug issues drm/nouveau/disp/dp: use new devinit script interpreter entry-point drm/nouveau/disp/dp: determine link bandwidth requirements from head state drm/nouveau/disp: introduce acquire/release display path methods ...
-rw-r--r--drivers/gpu/drm/nouveau/dispnv04/disp.h16
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl5070.h39
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h10
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h27
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_encoder.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hwmon.c983
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_vga.c4
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c244
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c13
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild24
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c243
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c24
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h14
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c65
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c140
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c652
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h (renamed from drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h)38
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c401
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c24
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c25
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c422
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c22
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c24
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c26
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c75
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c74
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c66
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h15
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c73
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c74
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c72
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c74
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c105
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h56
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c96
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c74
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c92
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c72
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h169
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c43
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c31
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c991
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h76
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c214
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h55
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c282
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h76
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c163
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h28
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c60
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c54
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c259
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c38
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c290
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c203
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c53
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c49
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c163
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c69
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c48
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c53
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c100
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c227
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c15
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c7
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c7
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c9
91 files changed, 4531 insertions, 4018 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h
index bea4543554ba..74a8795c2c2b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
@@ -169,18 +169,10 @@ static inline void
nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct dcb_output *outp, int crtc)
{
- struct nouveau_drm *drm = nouveau_drm(dev);
- struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
- struct nvbios_init init = {
- .subdev = &bios->subdev,
- .bios = bios,
- .offset = table,
- .outp = outp,
- .crtc = crtc,
- .execute = 1,
- };
-
- nvbios_exec(&init);
+ nvbios_init(&nvxx_bios(&nouveau_drm(dev)->client.device)->subdev, table,
+ init.outp = outp;
+ init.head = crtc;
+ );
}
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
index ae49dfd1f97b..542d95145a67 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
@@ -27,29 +27,25 @@ struct nv50_disp_scanoutpos_v0 {
struct nv50_disp_mthd_v1 {
__u8 version;
-#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
+#define NV50_DISP_MTHD_V1_ACQUIRE 0x01
+#define NV50_DISP_MTHD_V1_RELEASE 0x02
#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
-#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
-#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
#define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK 0x25
#define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI 0x26
-#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
__u8 method;
__u16 hasht;
__u16 hashm;
__u8 pad06[2];
};
-struct nv50_disp_dac_pwr_v0 {
+struct nv50_disp_acquire_v0 {
__u8 version;
- __u8 state;
- __u8 data;
- __u8 vsync;
- __u8 hsync;
- __u8 pad05[3];
+ __u8 or;
+ __u8 link;
+ __u8 pad03[5];
};
struct nv50_disp_dac_load_v0 {
@@ -59,12 +55,6 @@ struct nv50_disp_dac_load_v0 {
__u32 data;
};
-struct nv50_disp_sor_pwr_v0 {
- __u8 version;
- __u8 state;
- __u8 pad02[6];
-};
-
struct nv50_disp_sor_hda_eld_v0 {
__u8 version;
__u8 pad01[7];
@@ -76,7 +66,9 @@ struct nv50_disp_sor_hdmi_pwr_v0 {
__u8 state;
__u8 max_ac_packet;
__u8 rekey;
- __u8 pad04[4];
+ __u8 avi_infoframe_length;
+ __u8 vendor_infoframe_length;
+ __u8 pad06[2];
};
struct nv50_disp_sor_lvds_script_v0 {
@@ -86,12 +78,6 @@ struct nv50_disp_sor_lvds_script_v0 {
__u8 pad04[4];
};
-struct nv50_disp_sor_dp_pwr_v0 {
- __u8 version;
- __u8 state;
- __u8 pad02[6];
-};
-
struct nv50_disp_sor_dp_mst_link_v0 {
__u8 version;
__u8 state;
@@ -106,11 +92,4 @@ struct nv50_disp_sor_dp_mst_vcpi_v0 {
__u16 pbn;
__u16 aligned_pbn;
};
-
-struct nv50_disp_pior_pwr_v0 {
- __u8 version;
- __u8 state;
- __u8 type;
- __u8 pad03[5];
-};
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
index 970ae753968a..05f9c13ab8c3 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
@@ -8,17 +8,15 @@ struct nvkm_disp {
const struct nvkm_disp_func *func;
struct nvkm_engine engine;
- struct nvkm_oproxy *client;
-
+ struct list_head head;
+ struct list_head ior;
struct list_head outp;
struct list_head conn;
struct nvkm_event hpd;
struct nvkm_event vblank;
- struct {
- int nr;
- } head;
+ struct nvkm_oproxy *client;
};
int nv04_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
@@ -26,7 +24,9 @@ int nv50_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int g84_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gt200_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int g94_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int mcp77_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gt215_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int mcp89_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gf119_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gk104_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gk110_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
index 4dc1c8af840c..06ab48052128 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
@@ -3,19 +3,34 @@
struct nvbios_init {
struct nvkm_subdev *subdev;
- struct nvkm_bios *bios;
- u16 offset;
+ u32 offset;
+
struct dcb_output *outp;
- int crtc;
+ int or;
+ int link;
+ int head;
/* internal state used during parsing */
u8 execute;
u32 nested;
- u16 repeat;
- u16 repend;
+ u32 repeat;
+ u32 repend;
u32 ramcfg;
};
+#define nvbios_init(s,o,ARGS...) ({ \
+ struct nvbios_init init = { \
+ .subdev = (s), \
+ .offset = (o), \
+ .or = -1, \
+ .link = 0, \
+ .head = -1, \
+ .execute = 1, \
+ }; \
+ ARGS \
+ nvbios_exec(&init); \
+})
int nvbios_exec(struct nvbios_init *);
-int nvbios_init(struct nvkm_subdev *, bool execute);
+
+int nvbios_post(struct nvkm_subdev *, bool execute);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
index 820a4805916f..ff0709652f80 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
@@ -26,7 +26,6 @@ struct nvkm_timer {
u64 nvkm_timer_read(struct nvkm_timer *);
void nvkm_timer_alarm(struct nvkm_timer *, u32 nsec, struct nvkm_alarm *);
-void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *);
/* Delay based on GPU time (ie. PTIMER).
*
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 9a0772ad495a..b998c33af18a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -1533,7 +1533,8 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
if (conf & 0x100000)
entry->i2c_upper_default = true;
- entry->hasht = (entry->location << 4) | entry->type;
+ entry->hasht = (entry->extdev << 8) | (entry->location << 4) |
+ entry->type;
entry->hashm = (entry->heads << 8) | (link << 6) | entry->or;
return true;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index f802bcd94457..147b22163f9f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1045,6 +1045,9 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
return MODE_BAD;
}
+ if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
+ clock *= 2;
+
if (clock < min_clock)
return MODE_CLOCK_LOW;
@@ -1321,6 +1324,13 @@ nouveau_connector_create(struct drm_device *dev, int index)
break;
}
+ /* HDMI 3D support */
+ if ((disp->disp.oclass >= G82_DISP)
+ && ((type == DRM_MODE_CONNECTOR_DisplayPort)
+ || (type == DRM_MODE_CONNECTOR_eDP)
+ || (type == DRM_MODE_CONNECTOR_HDMIA)))
+ connector->st