diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-05-05 13:59:16 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-12 11:52:22 +0200 |
| commit | 8e46bc6370d08a21cc43bb747aef8ffae45df7d7 (patch) | |
| tree | 4758a240cc694c40ef59973258e617e677bf82a7 | |
| parent | 89b67a16a59b66b0dfb26307c5858e9cddcbb242 (diff) | |
arm64: dts: renesas: r9a08g046: Add wdt device node
The RZ/G3L SOC has 3 watchdog timer channels:
- channel0 (wdt0) for Cortex-A55-CPU Non-Secure,
- channel1 (wdt1) for Cortex-A55 CPU Secure,
- channel2 (wdt2) for Cortex-M33 CPU.
Add wdt0 node to RZ/G3L ("R9A08G046") SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505125921.149682-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 0cedf5a38291..02a3029c058e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -577,6 +577,20 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G046_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G046_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; stmmac_axi_setup: stmmac-axi-config { |