// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"
#include "mpfs-sev-kit-fabric.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Microchip PolarFire-SoC SEV Kit";
	compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";

	aliases {
		ethernet0 = &mac1;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		fabricbuf0ddrc: buffer@80000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x80000000 0x0 0x2000000>;
		};

		fabricbuf1ddrnc: buffer@c4000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xc4000000 0x0 0x4000000>;
		};

		fabricbuf2ddrncwcb: buffer@d4000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xd4000000 0x0 0x4000000>;
		};
	};

	ddrc_cache: memory@1000000000 {
		device_type = "memory";
		reg = <0x10 0x0 0x0 0x76000000>;
	};
};

&i2c0 {
	status = "okay";
};

&irqmux {
	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
			<12 &plic 25>, <13 &plic 26>,

			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,

			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
			<94 &plic 53>, <95 &plic 53>;
};

&gpio2 {
	status = "okay";
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	phy1: ethernet-phy@9 {
		reg = <9>;
	};
	phy0: ethernet-phy@8 {
		reg = <8>;
	};
};

&mac1 {
	status = "okay";
	phy-mode = "sgmii";
	phy-handle = <&phy1>;
};

&mbox {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};

&refclk {
	clock-frequency = <125000000>;
};

&rtc {
	status = "okay";
};

&syscontroller {
	status = "okay";
};

&usb {
	status = "okay";
	dr_mode = "otg";
};