From c9c4ddb20c427b19c6a2a1787bf82c7b2aac25c3 Mon Sep 17 00:00:00 2001 From: Petlozu Pravareshwar Date: Fri, 30 Sep 2022 16:02:13 +0000 Subject: soc/tegra: pmc: Add I/O pad table for Tegra234 Add I/O pad table for Tegra234 to allow configuring DPD mode and switching the pins to 1.8V or 3.3V as needed. On Tegra234, DPD registers are reorganized such that there is a DPD_REQ register and a DPD_STATUS register per pad group. Update the PMC driver accordingly. While at it, use the generated tables from tegra-pinmux-scripts to make the formatting of these tables more consistent. Signed-off-by: Petlozu Pravareshwar [treding@nvidia.com: generate tables from tegra-pinmux-scripts] Signed-off-by: Thierry Reding --- include/soc/tegra/pmc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index d186bccd125d..aadb845d281d 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -118,9 +118,9 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_2, TEGRA_IO_PAD_PEX_CNTRL, TEGRA_IO_PAD_PEX_CTL2, - TEGRA_IO_PAD_PEX_L0_RST_N, - TEGRA_IO_PAD_PEX_L1_RST_N, - TEGRA_IO_PAD_PEX_L5_RST_N, + TEGRA_IO_PAD_PEX_L0_RST, + TEGRA_IO_PAD_PEX_L1_RST, + TEGRA_IO_PAD_PEX_L5_RST, TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1_HV, -- cgit v1.2.3 From bebf683ba6829f544011411580bcd620b7581087 Mon Sep 17 00:00:00 2001 From: Kartik Date: Wed, 9 Nov 2022 19:50:22 +0530 Subject: soc/tegra: fuse: Use platform info with SoC revision Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik Reviewed-by: Arnd Bergmann Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- include/soc/tegra/fuse.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 977c334136e9..a63de5da8124 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -34,6 +34,20 @@ enum tegra_revision { TEGRA_REVISION_MAX, }; +enum tegra_platform { + TEGRA_PLATFORM_SILICON = 0, + TEGRA_PLATFORM_QT, + TEGRA_PLATFORM_SYSTEM_FPGA, + TEGRA_PLATFORM_UNIT_FPGA, + TEGRA_PLATFORM_ASIM_QT, + TEGRA_PLATFORM_ASIM_LINSIM, + TEGRA_PLATFORM_DSIM_ASIM_LINSIM, + TEGRA_PLATFORM_VERIFICATION_SIMULATION, + TEGRA_PLATFORM_VDK, + TEGRA_PLATFORM_VSP, + TEGRA_PLATFORM_MAX, +}; + struct tegra_sku_info { int sku_id; int cpu_process_id; @@ -47,6 +61,7 @@ struct tegra_sku_info { int gpu_speedo_id; int gpu_speedo_value; enum tegra_revision revision; + enum tegra_platform platform; }; #ifdef CONFIG_ARCH_TEGRA -- cgit v1.2.3 From b76bd1b36813a253f004d634e210d6e3909322c1 Mon Sep 17 00:00:00 2001 From: Manish Bhardwaj Date: Thu, 22 Sep 2022 15:56:27 +0530 Subject: firmware: tegra: include IVC header file only once Add the necessary definition to prevent compilation errors from the ivc.h file being included multiple times. This does not currently cause any compilation issues, but fix this anyway. Signed-off-by: Manish Bhardwaj Signed-off-by: Thierry Reding --- include/soc/tegra/ivc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/soc/tegra/ivc.h b/include/soc/tegra/ivc.h index 4aeb77cc22c5..88ce0bf439ad 100644 --- a/include/soc/tegra/ivc.h +++ b/include/soc/tegra/ivc.h @@ -4,6 +4,7 @@ */ #ifndef __TEGRA_IVC_H +#define __TEGRA_IVC_H #include #include -- cgit v1.2.3