e, 26 Aug 2036 18:37:30 GMT
ETag: "975eb47ee04dff81fcd3a98e0998fa7833d4f9cf"

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2009 - 2018 Intel Corporation. */

/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGBVF_H_
#define _IGBVF_H_

#include <linux/types.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>

#include "vf.h"

/* Forward declarations */
struct igbvf_info;
struct igbvf_adapter;

/* Interrupt defines */
#define IGBVF_START_ITR		488 /* ~8000 ints/sec */
#define IGBVF_4K_ITR		980
#define IGBVF_20K_ITR		196
#define IGBVF_70K_ITR		56

enum latency_range {
	lowest_latency = 0,
	low_latency = 1,
	bulk_latency = 2,
	latency_invalid = 255
};

/* Interrupt modes, as used by the IntMode parameter */
#define IGBVF_INT_MODE_LEGACY	0
#define IGBVF_INT_MODE_MSI	1
#define IGBVF_INT_MODE_MSIX	2

/* Tx/Rx descriptor defines */
#define IGBVF_DEFAULT_TXD	256
#define IGBVF_MAX_TXD		4096
#define IGBVF_MIN_TXD		80

#define IGBVF_DEFAULT_RXD	256
#define IGBVF_MAX_RXD		4096
#define IGBVF_MIN_RXD		80

#define IGBVF_MIN_ITR_USECS	10 /* 100000 irq/sec */
#define IGBVF_MAX_ITR_USECS	10000 /* 100    irq/sec */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *	   descriptors available in its onboard memory.
 *	   Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *	   available in host memory.
 *	   If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *	   descriptors until either it has this many to write back, or the
 *	   ITR timer expires.
 */
#define IGBVF_RX_PTHRESH	16
#define IGBVF_RX_HTHRESH	8
#define IGBVF_RX_WTHRESH	1

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE	1522

#define IGBVF_FC_PAUSE_TIME	0x0680 /* 858 usec */

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGBVF_TX_QUEUE_WAKE	32
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGBVF_RX_BUFFER_WRITE	16 /* Must be power of 2 */

#define AUTO_ALL_MODES		0
#define IGBVF_EEPROM_APME	0x0400

#define IGBVF_MNG_VLAN_NONE	(-1)

#define IGBVF_MAX_MAC_FILTERS	3

/* Number of packet split data buffers (not including the header buffer) */
#define PS_PAGE_BUFFERS		(MAX_PS_BUFFERS - 1)

enum igbvf_boards {
	board_vf,
	board_i350_vf,
};

struct igbvf_queue_stats {
	u64 packets;
	u64 bytes;
};

/* wrappers around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer
 */
struct igbvf_buffer {
	dma_addr_t dma;
	struct sk_buff *skb;
	union {
		/* Tx */
		struct {
			unsigned long time_stamp;
			union e1000_adv_tx_desc *next_to_watch;
			u16 length;
			u16 mapped_as_page;
		};
		/* Rx */
		struct {
			struct page *page;
			u64 page_dma;
			unsigned int page_offset;
		};
	};
};

union igbvf_desc {
	union e1000_adv_rx_desc rx_desc;
	union e1000_adv_tx_desc tx_desc;
	struct e1000_adv_tx_context_desc tx_context_desc;
};

struct igbvf_ring {
	struct igbvf_adapter *adapter;  /* backlink */
	union igbvf_desc *desc;	/* pointer to ring memory  */
	dma_addr_t dma;		/* phys address of ring    */
	unsigned int size;	/* length of ring in bytes */
	unsigned int count;	/* number of desc. in ring */

	u16 next_to_use;
	u16 next_to_clean;

	u16 head;
	u16 tail;

	/* array of buffer information structs */
	struct igbvf_buffer *buffer_info;
	struct napi_struct napi;

	char name[IFNAMSIZ + 5];
	u32 eims_value;
	u32 itr_val;
	enum latency_range itr_range;
	u16 itr_register;
	int set_itr;

	struct sk_buff *rx_skb_top;

	struct igbv