From a5cb804b68b4072e685bd76831ee647c489db4c8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 16 May 2023 15:46:14 +0200 Subject: firmware: xilinx: Switch Michal Simek's email to new one @xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/36d119221aa12369c601cd37160306aeb84fc973.1684244767.git.michal.simek@amd.com Signed-off-by: Greg Kroah-Hartman --- include/linux/firmware/xlnx-zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index f5da51677069..9dda7d9898ff 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -4,7 +4,7 @@ * * Copyright (C) 2014-2021 Xilinx * - * Michal Simek + * Michal Simek * Davorin Mista * Jolly Shah * Rajan Vaja -- cgit v1.2.3 l.h> #include #define BAR_0 0 #define BAR_1 1 #define INTEL_E1000_ETHERNET_DEVICE(device_id) {\ PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)} struct e1000_adapter; #include "e1000_hw.h" #define E1000_MAX_INTR 10 /* * Count for polling __E1000_RESET condition every 10-20msec. */ #define E1000_CHECK_RESET_COUNT 50 /* TX/RX descriptor defines */ #define E1000_DEFAULT_TXD 256 #define E1000_MAX_TXD 256 #define E1000_MIN_TXD 48 #define E1000_MAX_82544_TXD 4096 #define E1000_DEFAULT_RXD 256 #define E1000_MAX_RXD 256 #define E1000_MIN_RXD 48 #define E1000_MAX_82544_RXD 4096 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ /* this is the size past which hardware will drop packets when setting LPE=0 */ #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 /* Supported Rx Buffer Sizes */ #define E1000_RXBUFFER_128 128 /* Used for packet split */ #define E1000_RXBUFFER_256 256 /* Used for packet split */ #define E1000_RXBUFFER_512 512 #define E1000_RXBUFFER_1024 1024 #define E1000_RXBUFFER_2048 2048 #define E1000_RXBUFFER_4096 4096 #define E1000_RXBUFFER_8192 8192 #define E1000_RXBUFFER_16384 16384 /* SmartSpeed delimiters */ #define E1000_SMARTSPEED_DOWNSHIFT 3 #define E1000_SMARTSPEED_MAX 15 /* Packet Buffer allocations */ #define E1000_PBA_BYTES_SHIFT 0xA #define E1000_TX_HEAD_ADDR_SHIFT 7 #define E1000_PBA_TX_MASK 0xFFFF0000 /* Flow Control Watermarks */ #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ #define E1000_FC_PAUSE_TIME 0xFFFF /* pause for the max or until send xon */ /* How many Tx Descriptors do we need to call netif_wake_queue ? */ #define E1000_TX_QUEUE_WAKE 16 /* How many Rx Buffers do we bundle into one write to the hardware ? */ #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ #define AUTO_ALL_MODES 0 #define E1000_EEPROM_82544_APM 0x0004 #define E1000_EEPROM_APME 0x0400 #ifndef E1000_MASTER_SLAVE /* Switch to override PHY master/slave setting */ #define E1000_MASTER_SLAVE e1000_ms_hw_default #endif #define E1000_MNG_VLAN_NONE (-1) /* wrapper around a pointer to a socket buffer, * so a DMA handle can be stored along with the buffer */ struct e1000_tx_buffer { struct sk_buff *skb; dma_addr_t dma; unsigned long time_stamp; u16 length; u16 next_to_watch; bool mapped_as_page; unsigned short segs; unsigned int bytecount; }; struct e1000_rx_buffer { union { struct page *page; /* jumbo: alloc_page */ u8 *data; /* else,