From 53b963b603d7839556ea51cbb1db755882796e95 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Thu, 27 Oct 2016 17:48:49 +0800 Subject: drm/amd/powerplay: add new bit mask to ctrl clock stretch feature. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 9e49f2777143..a50765d18949 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -1428,7 +1428,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDCI); - if ((hwmgr->pp_table_version != PP_TABLE_V0) + if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) && (table_info->cac_dtp_table->usClockStretchAmount != 0)) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher); diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index e38b999e3235..36effa19abdd 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -85,7 +85,8 @@ enum PP_FEATURE_MASK { PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, PP_VBI_TIME_SUPPORT_MASK = 0x80, PP_ULV_MASK = 0x100, - PP_ENABLE_GFX_CG_THRU_SMU = 0x200 + PP_ENABLE_GFX_CG_THRU_SMU = 0x200, + PP_CLOCK_STRETCH_MASK = 0x400, }; enum PHM_BackEnd_Magic { -- cgit v1.2.3 From a08d8c929f770d16fcff04ee0c30a29270cc2b94 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Thu, 27 Oct 2016 17:54:01 +0800 Subject: drm/amd/powerplay: make CAC feature controlled by module parameter. use same module parameter with powercontainment Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2ba7937d2545..2ada52f54a47 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -692,13 +692,17 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); - if (amdgpu_powercontainment) + if (amdgpu_powercontainment) { phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); - else + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + } else { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); - + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + } hwmgr->feature_mask = amdgpu_pp_feature_mask; return 0; @@ -733,9 +737,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot); @@ -765,8 +766,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); return 0; } @@ -789,9 +788,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - return 0; } @@ -807,8 +803,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_TCPRamping); phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV); return 0; -- cgit v1.2.3 From a414cd708b1617d6b31acdc74a6cfecbae2a172f Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Sun, 30 Oct 2016 23:05:47 +0800 Subject: drm/amdgpu: cleanup amdgpu_cs_ioctl to make code logicality clear MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Huang Rui Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 78da52f90099..15c56c825b86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1054,29 +1054,29 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_init(&parser, data); if (r) { DRM_ERROR("Failed to initialize parser !\n"); - amdgpu_cs_parser_fini(&parser, r, false); - r = amdgpu_cs_handle_lockup(adev, r); - return r; - } - r = amdgpu_cs_parser_bos(&parser, data); - if (r == -ENOMEM) - DRM_ERROR("Not enough memory for command submission!\n"); - else if (r && r != -ERESTARTSYS) - DRM_ERROR("Failed to process the buffer list %d!\n", r); - else if (!r) { - reserved_buffers = true; - r = amdgpu_cs_ib_fill(adev, &parser); + goto out; } - if (!r) { - r = amdgpu_cs_dependencies(adev, &parser); - if (r) - DRM_ERROR("Failed in the dependencies handling %d!\n", r); + r = amdgpu_cs_parser_bos(&parser, data); + if (r) { + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else if (r != -ERESTARTSYS) + DRM_ERROR("Failed to process the buffer list %d!\n", r); + goto out; } + reserved_buffers = true; + r = amdgpu_cs_ib_fill(adev, &parser); if (r) goto out; + r = amdgpu_cs_dependencies(adev, &parser); + if (r) { + DRM_ERROR("Failed in the dependencies handling %d!\n", r); + goto out; + } + for (i = 0; i < parser.job->num_ibs; i++) trace_amdgpu_cs(&parser, i); -- cgit v1.2.3 From 47ecd3c4e09ee8dfd1dbd2728278ccec78ab43b9 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Mon, 31 Oct 2016 17:00:21 +0800 Subject: drm/amdgpu: remove amdgpu_cs_handle_lockup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In fence waiting, it never return -EDEADLK yet, so drop this function here. Signed-off-by: Huang Rui Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 15c56c825b86..5a277495d6a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -841,16 +841,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, return amdgpu_cs_sync_rings(p); } -static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) -{ - if (r == -EDEADLK) { - r = amdgpu_gpu_reset(adev); - if (!r) - r = -EAGAIN; - } - return r; -} - static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, struct amdgpu_cs_parser *parser) { @@ -1088,7 +1078,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) out: amdgpu_cs_parser_fini(&parser, r, reserved_buffers); - r = amdgpu_cs_handle_lockup(adev, r); return r; } -- cgit v1.2.3 From 72a16a9d59ee0de87d9899959978b8e8f6da8438 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Sat, 29 Oct 2016 23:28:58 +0300 Subject: drm/amd/powerplay: export a function to read fan rpm Powerplay hwmgr already has an implementation, all we need to do is to call it. Signed-off-by: Grazvydas Ignotas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 1 + 2 files changed, 19 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 0b1f2205c2f1..1f497647a920 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -582,6 +582,23 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); } +static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) +{ + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); +} + static int pp_dpm_get_temperature(void *handle) { struct pp_hwmgr *hwmgr; @@ -852,6 +869,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { .get_fan_control_mode = pp_dpm_get_fan_control_mode, .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, + .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, .get_pp_num_states = pp_dpm_get_pp_num_states, .get_pp_table = pp_dpm_get_pp_table, .set_pp_table = pp_dpm_set_pp_table, diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index eb3e83d7af31..2892b4e3948d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -349,6 +349,7 @@ struct amd_powerplay_funcs { int (*get_fan_control_mode)(void *handle); int (*set_fan_speed_percent)(void *handle, uint32_t percent); int (*get_fan_speed_percent)(void *handle, uint32_t *speed); + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); int (*get_pp_num_states)(void *handle, struct pp_states_info *data); int (*get_pp_table)(void *handle, char **table); int (*set_pp_table)(void *handle, const char *buf, size_t size); -- cgit v1.2.3 From 81c1514bf8db9aee71bc6e610a62d64a865e06a4 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Sat, 29 Oct 2016 23:28:59 +0300 Subject: drm/amd/amdgpu: expose fan rpm though hwmon Only for cards that are supported by powerplay. Signed-off-by: Grazvydas Ignotas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index bd85e35998e7..e45bd052157b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -317,6 +317,11 @@ struct amdgpu_dpm_funcs { (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) +#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \ + -EINVAL) + #define amdgpu_dpm_get_sclk(adev, l) \ ((adev)->pp_enabled ? \ (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 274f3309aec9..723ae682bf25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -737,6 +737,21 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, return sprintf(buf, "%i\n", speed); } +static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + u32 speed; + + err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); + if (err) + return err; + + return sprintf(buf, "%i\n", speed); +} + static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); @@ -744,6 +759,7 @@ static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); +static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_temp1_input.dev_attr.attr, @@ -753,6 +769,7 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_min.dev_attr.attr, &sensor_dev_attr_pwm1_max.dev_attr.attr, + &sensor_dev_attr_fan1_input.dev_attr.attr, NULL }; @@ -804,6 +821,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) return 0; + /* requires powerplay */ + if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr) + return 0; + return effective_mode; } -- cgit v1.2.3 From f8bdce3e868742f32ebab2e377fb35ace47415c4 Mon Sep 17 00:00:00 2001 From: Maruthi Srinivas Bayyavarapu Date: Mon, 31 Oct 2016 19:41:55 +0530 Subject: drm/amdgpu: enable UVD clockgating in Polaris-10/11 UVD clocks are set to be disabled, when not in use. Signed-off-by: Maruthi Bayyavarapu Reviewed-by: Alex Deucher Reviewed-by: Tom StDenis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 52d0a83e6ad1..820af9293655 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -934,12 +934,12 @@ static int vi_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x14; break; case CHIP_POLARIS11: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x5A; break; case CHIP_POLARIS10: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; break; -- cgit v1.2.3 From 2068751d094104ab3f396c754ffc65058340f70e Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Mon, 31 Oct 2016 02:51:18 -0400 Subject: drm/amdgpu: Add a ring type KIQ definition Add a new ring type definition for KIQ. KIQ is used for interaction between driver and CP. Signed-off-by: Xiangliang Yu Signed-off-by: Trigger Huang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index f2ad49c8e85b..574f0b79c690 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -44,7 +44,8 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_COMPUTE, AMDGPU_RING_TYPE_SDMA, AMDGPU_RING_TYPE_UVD, - AMDGPU_RING_TYPE_VCE + AMDGPU_RING_TYPE_VCE, + AMDGPU_RING_TYPE_KIQ }; struct amdgpu_device; -- cgit v1.2.3 From e22504425f72cf8a6d43884e4080e534e4919e61 Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Wed, 2 Nov 2016 05:43:44 -0400 Subject: drm/amdgpu:no gpu scheduler for KIQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit KIQ is used for interaction between driver and CP, and not exposed to outside client, as such it doesn't need to be handled by GPU scheduler. Signed-off-by: Monk Liu Signed-off-by: Xiangliang Yu Signed-off-by: Trigger Huang Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 39 +++++++++++++++++-------------- 1 file changed, 21 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 97928d7281f6..7b60fb79c3a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, if (!ring->fence_drv.fences) return -ENOMEM; - timeout = msecs_to_jiffies(amdgpu_lockup_timeout); - if (timeout == 0) { - /* - * FIXME: - * Delayed workqueue cannot use it directly, - * so the scheduler will not use delayed workqueue if - * MAX_SCHEDULE_TIMEOUT is set. - * Currently keep it simple and silly. - */ - timeout = MAX_SCHEDULE_TIMEOUT; - } - r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, - num_hw_submission, - timeout, ring->name); - if (r) { - DRM_ERROR("Failed to create scheduler on ring %s.\n", - ring->name); - return r; + /* No need to setup the GPU scheduler for KIQ ring */ + if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { + timeout = msecs_to_jiffies(amdgpu_lockup_timeout); + if (timeout == 0) { + /* + * FIXME: + * Delayed workqueue cannot use it directly, + * so the scheduler will not use delayed workqueue if + * MAX_SCHEDULE_TIMEOUT is set. + * Currently keep it simple and silly. + */ + timeout = MAX_SCHEDULE_TIMEOUT; + } + r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, + num_hw_submission, + timeout, ring->name); + if (r) { + DRM_ERROR("Failed to create scheduler on ring %s.\n", + ring->name); + return r; + } } return 0; -- cgit v1.2.3 From acd546b9fda695e97473d0fb8e744aba6b274789 Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Thu, 28 Apr 2016 15:22:54 +0800 Subject: drm/amdgpu:bypass avfs event manager for sriov This patch is used for virtualization support. In virtualization case, the initialization sequences are not totally the same as non-Virtualization's. The avfs event manager should be bypassed if in SRIOV virtualization case. At the same, this patch will also bypass starting SMC within SRIOV in FIJI, so the SMU firmware loading will be avoid, which is required in SRIOV. Signed-off-by: Frank Min Signed-off-by: Xiangliang Yu Signed-off-by: Trigger Huang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c index b86e48fb40d1..26eff56b4a99 100755 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -396,7 +396,8 @@ static int fiji_start_smu(struct pp_smumgr *smumgr) struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!(smu7_is_smc_ram_running(smumgr) + || cgs_is_virtualization_enabled(smumgr->device))) { fiji_avfs_event_mgr(smumgr, false); /* Check if SMU is running in protected mode */ @@ -443,6 +444,9 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) uint32_t efuse = 0; uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; + if (cgs_is_virtualization_enabled(smumgr->device)) + return 0; + if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, mask, &efuse)) { if (efuse) -- cgit v1.2.3 From ba5f884cfa3d7fef06b9487679cc8472bf51aa25 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Thu, 27 Oct 2016 15:29:57 +0800 Subject: drm/amdgpu/powerplay: pp module only enable smu when dpm disabled. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 6 +-- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 51 +++++++++++++++++------ drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 2 + 3 files changed, 44 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index fa6baf31a35d..e2f0507eaac1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle) ret = adev->powerplay.ip_funcs->sw_init( adev->powerplay.pp_handle); - if (adev->pp_enabled) - adev->pm.dpm_enabled = true; - return ret; } @@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle) ret = adev->powerplay.ip_funcs->hw_init( adev->powerplay.pp_handle); + if (amdgpu_dpm != 0) + adev->pm.dpm_enabled = true; + return ret; } diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 1f497647a920..4a4f97b37dcb 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -41,7 +41,7 @@ #define PP_CHECK_HW(hwmgr) \ do { \ if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ - return -EINVAL; \ + return 0; \ } while (0) static int pp_early_init(void *handle) @@ -115,6 +115,7 @@ static int pp_hw_init(void *handle) struct pp_instance *pp_handle; struct pp_smumgr *smumgr; struct pp_eventmgr *eventmgr; + struct pp_hwmgr *hwmgr; int ret = 0; if (handle == NULL) @@ -122,6 +123,7 @@ static int pp_hw_init(void *handle) pp_handle = (struct pp_instance *)handle; smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; if (smumgr == NULL || smumgr->smumgr_funcs == NULL || smumgr->smumgr_funcs->smu_init == NULL || @@ -141,9 +143,11 @@ static int pp_hw_init(void *handle) return ret; } - hw_init_power_state_table(pp_handle->hwmgr); - eventmgr = pp_handle->eventmgr; + PP_CHECK_HW(hwmgr); + hw_init_power_state_table(hwmgr); + + eventmgr = pp_handle->eventmgr; if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) return -EINVAL; @@ -243,7 +247,9 @@ static int pp_suspend(void *handle) pp_handle = (struct pp_instance *)handle; eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); + + if (eventmgr != NULL) + pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); return 0; } @@ -273,7 +279,8 @@ static int pp_resume(void *handle) } eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); + if (eventmgr != NULL) + pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); return 0; } @@ -340,8 +347,7 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); return (((struct pp_instance *)handle)->hwmgr->dpm_level); } @@ -448,6 +454,9 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, if (pp_handle == NULL) return -EINVAL; + if (pp_handle->eventmgr == NULL) + return 0; + switch (event_id) { case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); @@ -899,6 +908,12 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init, if (ret) goto fail_smum; + + amd_pp->pp_handle = handle; + + if (amdgpu_dpm == 0) + return 0; + ret = hwmgr_init(pp_init, handle); if (ret) goto fail_hwmgr; @@ -907,7 +922,6 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init, if (ret) goto fail_eventmgr; - amd_pp->pp_handle = handle; return 0; fail_eventmgr: @@ -926,12 +940,12 @@ static int amd_pp_instance_fini(void *handle) if (instance == NULL) return -EINVAL; - eventmgr_fini(instance->eventmgr); - - hwmgr_fini(instance->hwmgr); + if (amdgpu_dpm != 0) { + eventmgr_fini(instance->eventmgr); + hwmgr_fini(instance->hwmgr); + } smum_fini(instance->smu_mgr); - kfree(handle); return 0; } @@ -990,6 +1004,9 @@ int amd_powerplay_reset(void *handle) hw_init_power_state_table(instance->hwmgr); + if (amdgpu_dpm == 0) + return 0; + if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) return -EINVAL; @@ -1011,6 +1028,8 @@ int amd_powerplay_display_configuration_change(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + phm_store_dal_configuration_data(hwmgr, display_config); return 0; @@ -1028,6 +1047,8 @@ int amd_powerplay_get_display_power_level(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + return phm_get_dal_power_level(hwmgr, output); } @@ -1045,6 +1066,8 @@ int amd_powerplay_get_current_clocks(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + phm_get_dal_power_level(hwmgr, &simple_clocks); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { @@ -1089,6 +1112,8 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + result = phm_get_clock_by_type(hwmgr, type, clocks); return result; @@ -1107,6 +1132,8 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) result = phm_get_max_high_clocks(hwmgr, clocks); diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 2892b4e3948d..3a883e6c601a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,6 +29,8 @@ #include "amd_shared.h" #include "cgs_common.h" +extern int amdgpu_dpm; + enum amd_pp_sensors { AMDGPU_PP_SENSOR_GFX_SCLK = 0, AMDGPU_PP_SENSOR_VDDNB, -- cgit v1.2.3 From 55ff54837845ddb5387e70b0ae1231e499b85c69 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 2 Nov 2016 13:24:02 +0800 Subject: drm/amd/powerplay: use mask bit for deepsleep/power tune feature. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++-- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2ada52f54a47..febee267ff7c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -685,14 +685,14 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) { - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); else phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); - if (amdgpu_powercontainment) { + if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) { phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); phm_cap_set(hwmgr->platform_descriptor.platformCaps, diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 36effa19abdd..a57410bf9f37 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -38,8 +38,6 @@ struct pp_hwmgr; struct phm_fan_speed_info; struct pp_atomctrl_voltage_table; -extern int amdgpu_powercontainment; -extern int amdgpu_sclk_deep_sleep_en; extern unsigned amdgpu_pp_feature_mask; #define VOLTAGE_SCALE 4 -- cgit v1.2.3 From 801caaf66309fdd084fc170dc1bea5140389747a Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 2 Nov 2016 13:35:15 +0800 Subject: drm/amdgpu: use mask bit for deep sleep feature on dpm. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 2 ++ drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 2 +- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 2 +- drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index e45bd052157b..955d6f21e2b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -52,6 +52,8 @@ enum amdgpu_dpm_event_src { AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 }; +#define SCLK_DEEP_SLEEP_MASK 0x8 + struct amdgpu_ps { u32 caps; /* vbios flags */ u32 class; /* vbios flags */ diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 1caff75ab9fc..bd690a21fdfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -5896,7 +5896,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) pi->pcie_dpm_key_disabled = 0; pi->thermal_sclk_dpm_enabled = 0; - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 352b5fad5a06..41fa351aa241 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev) pi->caps_td_ramping = true; pi->caps_tcp_ramping = true; } - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 61172d4a0657..5a1bc358bcb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -2845,7 +2845,7 @@ static int kv_dpm_init(struct amdgpu_device *adev) pi->caps_tcp_ramping = true; } - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; -- cgit v1.2.3 From 3ca67300acb510f3d79688eb3c7c74d3d1984e9a Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 2 Nov 2016 13:38:37 +0800 Subject: drm/amdgpu: delete duplicate module parameter. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c2b8496cdf63..7a94a3ce94e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -92,13 +92,13 @@ extern int amdgpu_vm_debug; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_powerplay; -extern int amdgpu_powercontainment; +extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern unsigned amdgpu_pcie_gen_cap; extern unsigned amdgpu_pcie_lane_cap; extern unsigned amdgpu_cg_mask; extern unsigned amdgpu_pg_mask; extern char *amdgpu_disable_cu; -extern int amdgpu_sclk_deep_sleep_en; extern char *amdgpu_virtual_display; extern unsigned amdgpu_pp_feature_mask; extern int amdgpu_vram_page_split; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6bb4d9e9afe4..3210081e3c49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -91,8 +91,8 @@ int amdgpu_exp_hw_support = 0; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_powerplay = -1; -int amdgpu_powercontainment = 1; -int amdgpu_sclk_deep_sleep_en = 1; +int amdgpu_no_evict = 0; +int amdgpu_direct_gma_size = 0; unsigned amdgpu_pcie_gen_cap = 0; unsigned amdgpu_pcie_lane_cap = 0; unsigned amdgpu_cg_mask = 0xffffffff; @@ -182,14 +182,14 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); module_param_named(powerplay, amdgpu_powerplay, int, 0444); -MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); -module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); - MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); -MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); -module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); -- cgit v1.2.3 From ce4286bfa7123d779a58c3b88481bf6dc0a54090 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 2 Nov 2016 14:53:04 +0800 Subject: drm/amd/powerplay: fix code style Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c index 41b634ffa5b0..26477f0f09dc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c @@ -603,9 +603,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) return 0; } -static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) +static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, + uint32_t target_tdp) { - return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); } -- cgit v1.2.3 From 4c696ecf4f87617f3bfd8fb8ecf20e879b635954 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 2 Nov 2016 16:03:46 +0800 Subject: drm/amd/powerplay: enable voltage control by default for dgpu. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index febee267ff7c..356b7c437022 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) switch (hwmgr->chip_id) { case CHIP_TOPAZ: topaz_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK | + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); hwmgr->pp_table_version = PP_TABLE_V0; break; case CHIP_TONGA: tonga_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK); + hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; break; case CHIP_FIJI: fiji_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK | + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); break; case CHIP_POLARIS11: -- cgit v1.2.3 From dc2f8a9aa98c5983d5faacf7e9843f8d15b5da9c Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 2 Nov 2016 16:05:08 +0800 Subject: drm/amd/powerplay: delete duplicate code in smu7_hwmgr.c Voltage Controller have been enabled (SMC message) before ULV enablement. Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index a50765d18949..e22046507e77 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -993,13 +993,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_Voltage_Cntl_Enable)), - "Failed to enable voltage DPM during DPM Start Function!", - return -EINVAL); - - if (smu7_enable_sclk_mclk_dpm(hwmgr)) { printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); return -EINVAL; -- cgit v1.2.3 From aa4747c00a2dd034c5fdf70ca73b1674ca15beb3 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 4 Nov 2016 20:35:46 +0800 Subject: drm/amdgpu: refine uvd_4.2 clock gate sequence. 1. partial revert commit 91db308d6e96. not set uvd bypass mode. 2. enable uvd cg before initialize uvd. 3. set uvd clock to default value 100MHz. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 8 ------- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 40 ++++++++--------------------------- 2 files changed, 9 insertions(+), 39 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index bd690a21fdfa..fe42e2fb2622 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) if (!gate) { /* turn the clocks on when decoding */ - ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); - if (ret) - return ret; - if (pi->caps_uvd_dpm || (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) pi->smc_state_table.UvdBootLevel = 0; @@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) ret = ci_enable_uvd_dpm(adev, false); if (ret) return ret; - - ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); } return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 8f9c7d55ddda..d2c96f1f1475 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -45,7 +45,8 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v4_2_start(struct amdgpu_device *adev); static void uvd_v4_2_stop(struct amdgpu_device *adev); - +static int uvd_v4_2_set_clockgating_state(void *handle, + enum amd_clockgating_state state); /** * uvd_v4_2_ring_get_rptr - get read pointer * @@ -154,9 +155,9 @@ static int uvd_v4_2_hw_init(void *handle) uint32_t tmp; int r; - /* raise clocks while booting up the VCPU */ - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - + uvd_v4_2_init_cg(adev); + uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE); + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); r = uvd_v4_2_start(adev); if (r) goto done; @@ -196,8 +197,6 @@ static int uvd_v4_2_hw_init(void *handle) amdgpu_ring_commit(ring); done: - /* lower clocks again */ - amdgpu_asic_set_uvd_clocks(adev, 0, 0); if (!r) DRM_INFO("UVD initialized successfully.\n"); @@ -274,9 +273,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev) uvd_v4_2_mc_resume(adev); - /* disable clock gating */ - WREG32(mmUVD_CGC_GATE, 0); - /* disable interupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); @@ -568,8 +564,6 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); - - uvd_v4_2_init_cg(adev); } static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, @@ -579,7 +573,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); - data = 0xfff; + data |= 0xfff; WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); orig = data = RREG32(mmUVD_CGC_CTRL); @@ -686,34 +680,18 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, return 0; } -static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) -{ - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); - - if (enable) - tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - else - tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); -} - static int uvd_v4_2_set_clockgating_state(void *handle, enum amd_clockgating_state state) { bool gate = false; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMD_CG_STATE_GATE) - gate = true; - - uvd_v5_0_set_bypass_mode(adev, gate); - if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; + if (state == AMD_CG_STATE_GATE) + gate = true; + uvd_v4_2_enable_mgcg(adev, gate); return 0; -- cgit v1.2.3 From 061995540d267787047f0968bfc5de7c8149b354 Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Tue, 11 Oct 2016 13:21:11 +0800 Subject: drm/amd/powerplay:Tonga not to start SMC if SRIOV This patch is used for virtualization support. In virtualization case, Tonga SMC should not be started and SMU firmware should not be loaded if in SRIOV environment. The same operation will be applied on FIJI in other patch. Signed-off-by: Monk Liu Signed-off-by: Trigger Huang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index 5f9124046b9b..eff9a232e72e 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -140,7 +140,8 @@ static int tonga_start_smu(struct pp_smumgr *smumgr) int result; /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!(smu7_is_smc_ram_running(smumgr) || + cgs_is_virtualization_enabled(smumgr->device))) { /*Check if SMU is running in protected mode*/ if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)) { -- cgit v1.2.3 From 526bae372c1f1b2932b5bd3be01a47f604fbc97d Mon Sep 17 00:00:00 2001 From: jimqu Date: Mon, 7 Nov 2016 09:53:10 +0800 Subject: drm/amdgpu: fix logic error for checking amdgpu_vram_page_split MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: JimQu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9e16e975f31a..91d30f2e05ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1030,8 +1030,8 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_vm_block_size = 9; } - if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) || - !amdgpu_check_pot_argument(amdgpu_vram_page_split)) { + if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || + !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { dev_warn(adev->dev, "invalid VRAM page split (%d)\n", amdgpu_vram_page_split); amdgpu_vram_page_split = 1024; -- cgit v1.2.3 From 4098e6cd610625a0c786f71bab291cf7003d32cc Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Mon, 7 Nov 2016 10:32:50 -0500 Subject: drm/amd/amdgpu: Clean up wave gfx7 helper De-numberify indirect register access for gfx v7. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 5b631fd1a879..06fddba54445 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4359,7 +4359,11 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { - WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); return RREG32(mmSQ_IND_DATA); } -- cgit v1.2.3 From bc24fbe9df6623500ad1fab92e71265d4cb7fa2a Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Mon, 7 Nov 2016 10:33:47 -0500 Subject: drm/amd/amdgpu: Clean up wave gfx8 helper De-numberify indirect register access for gfx v8. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 23f1bc94ad3e..1ac88b1fb1a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5442,7 +5442,11 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { - WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); return RREG32(mmSQ_IND_DATA); } -- cgit v1.2.3 From 3f12325ab8dc3a35f77eaf0155bd6d6e78f67e9c Mon Sep 17 00:00:00 2001 From: Ravikant B Sharma Date: Tue, 8 Nov 2016 11:19:42 +0530 Subject: drm/amd/amdgpu : Fix NULL pointer comparison MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace direct comparisons to NULL i.e. 'x == NULL' with '!x'. As per coding standard. Reviewed-by: Christian König Signed-off-by: Ravikant B Sharma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 2b6afe123f3d..b7e2762fcdd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -70,7 +70,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) return false; } adev->bios = kmalloc(size, GFP_KERNEL); - if (adev->bios == NULL) { + if (!adev->bios) { iounmap(bios); return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index 34a795463988..de9f919ae336 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -327,9 +327,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, return -EINVAL; *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL); - if ((*sa_bo) == NULL) { + if (!(*sa_bo)) return -ENOMEM; - } (*sa_bo)->manager = sa_manager; (*sa_bo)->fence = NULL; INIT_LIST_HEAD(&(*sa_bo)->olist); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 1ac88b1fb1a1..ab84bff18727 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3904,7 +3904,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) int list_size; unsigned int *register_list_format = kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); - if (register_list_format == NULL) + if (!register_list_format) return -ENOMEM; memcpy(register_list_format, adev->gfx.rlc.register_list_format, adev->gfx.rlc.reg_list_format_size_bytes); -- cgit v1.2.3 From de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Wed, 26 Oct 2016 11:58:25 -0400 Subject: drm/amd/amdgpu: Introduction of SI registers (v2) This introduces the SI registers in the amdgpu driver style. v2: squash duplicates fix Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h | 661 + .../drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h | 8127 ++++++++++++ .../gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 4445 +++++++ .../drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h | 9836 ++++++++++++++ .../gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h | 1760 +++ .../drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h | 12821 +++++++++++++++++++ .../gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h | 1274 ++ .../drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h | 11895 +++++++++++++++++ .../gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h | 272 + .../drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h | 1079 ++ .../gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h | 148 + .../drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h | 715 ++ .../gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h | 96 + .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 795 ++ .../gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h | 64 + .../drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h | 99 + 16 files changed, 54087 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h new file mode 100644 index 000000000000..7138fbf7256a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h @@ -0,0 +1,661 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_3_0_D_H +#define BIF_3_0_D_H + +#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C +#define ixPB0_DFT_JIT_INJ_REG0 0x13000 +#define ixPB0_DFT_JIT_INJ_REG1 0x13004 +#define ixPB0_DFT_JIT_INJ_REG2 0x13008 +#define ixPB0_GLB_CTRL_REG0 0x10004 +#define ixPB0_GLB_CTRL_REG1 0x10008 +#define ixPB0_GLB_CTRL_REG2 0x1000C +#define ixPB0_GLB_CTRL_REG3 0x10010 +#define ixPB0_GLB_CTRL_REG4 0x10014 +#define ixPB0_GLB_CTRL_REG5 0x10018 +#define ixPB0_GLB_OVRD_REG0 0x10030 +#define ixPB0_GLB_OVRD_REG1 0x10034 +#define ixPB0_GLB_OVRD_REG2 0x10038 +#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C +#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020 +#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024 +#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028 +#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C +#define ixPB0_HW_DEBUG 0x12004 +#define ixPB0_PIF_CNTL 0x0010 +#define ixPB0_PIF_CNTL2 0x0014 +#define ixPB0_PIF_HW_DEBUG 0x0002 +#define ixPB0_PIF_PAIRING 0x0011 +#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020 +#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032 +#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021 +#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033 +#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034 +#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035 +#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036 +#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037 +#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022 +#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023 +#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024 +#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025 +#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026 +#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027 +#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030 +#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031 +#define ixPB0_PIF_PWRDOWN_0 0x0012 +#define ixPB0_PIF_PWRDOWN_1 0x0013 +#define ixPB0_PIF_PWRDOWN_2 0x0017 +#define ixPB0_PIF_PWRDOWN_3 0x0018 +#define ixPB0_PIF_SC_CTL 0x0016 +#define ixPB0_PIF_SCRATCH 0x0001 +#define ixPB0_PIF_SEQ_STATUS_0 0x0028 +#define ixPB0_PIF_SEQ_STATUS_10 0x003A +#define ixPB0_PIF_SEQ_STATUS_1 0x0029 +#define ixPB0_PIF_SEQ_STATUS_11 0x003B +#define ixPB0_PIF_SEQ_STATUS_12 0x003C +#define ixPB0_PIF_SEQ_STATUS_13 0x003D +#define ixPB0_PIF_SEQ_STATUS_14 0x003E +#define ixPB0_PIF_SEQ_STATUS_15 0x003F +#define ixPB0_PIF_SEQ_STATUS_2 0x002A +#define ixPB0_PIF_SEQ_STATUS_3 0x002B +#define ixPB0_PIF_SEQ_STATUS_4 0x002C +#define ixPB0_PIF_SEQ_STATUS_5 0x002D +#define ixPB0_PIF_SEQ_STATUS_6 0x002E +#define ixPB0_PIF_SEQ_STATUS_7 0x002F +#define ixPB0_PIF_SEQ_STATUS_8 0x0038 +#define ixPB0_PIF_SEQ_STATUS_9 0x0039 +#define ixPB0_PIF_TXPHYSTATUS 0x0015 +#define ixPB0_PLL_LC0_CTRL_REG0 0x14480 +#define ixPB0_PLL_LC0_OVRD_REG0 0x14490 +#define ixPB0_PLL_LC0_OVRD_REG1 0x14494 +#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 +#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 +#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 +#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C +#define ixPB0_PLL_RO0_CTRL_REG0 0x14440 +#define ixPB0_PLL_RO0_OVRD_REG0 0x14450 +#define ixPB0_PLL_RO0_OVRD_REG1 0x14454 +#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 +#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 +#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 +#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C +#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000 +#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010 +#define ixPB0_RX_GLB_CTRL_REG0 0x16000 +#define ixPB0_RX_GLB_CTRL_REG1 0x16004 +#define ixPB0_RX_GLB_CTRL_REG2 0x16008 +#define ixPB0_RX_GLB_CTRL_REG3 0x1600C +#define ixPB0_RX_GLB_CTRL_REG4 0x16010 +#define ixPB0_RX_GLB_CTRL_REG5 0x16014 +#define ixPB0_RX_GLB_CTRL_REG6 0x16018 +#define ixPB0_RX_GLB_CTRL_REG7 0x1601C +#define ixPB0_RX_GLB_CTRL_REG8 0x16020 +#define ixPB0_RX_GLB_OVRD_REG0 0x16030 +#define ixPB0_RX_GLB_OVRD_REG1 0x16034 +#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 +#define ixPB0_RX_LANE0_CTRL_REG0 0x16440 +#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 +#define ixPB0_RX_LANE10_CTRL_REG0 0x17500 +#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 +#define ixPB0_RX_LANE11_CTRL_REG0 0x17600 +#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 +#define ixPB0_RX_LANE12_CTRL_REG0 0x17840 +#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 +#define ixPB0_RX_LANE13_CTRL_REG0 0x17880 +#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 +#define ixPB0_RX_LANE14_CTRL_REG0 0x17900 +#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 +#define ixPB0_RX_LANE15_CTRL_REG0 0x17A00 +#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 +#define ixPB0_RX_LANE1_CTRL_REG0 0x16480 +#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 +#define ixPB0_RX_LANE2_CTRL_REG0 0x16500 +#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 +#define ixPB0_RX_LANE3_CTRL_REG0 0x16600 +#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 +#define ixPB0_RX_LANE4_CTRL_REG0 0x16800 +#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 +#define ixPB0_RX_LANE5_CTRL_REG0 0x16880 +#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 +#define ixPB0_RX_LANE6_CTRL_REG0 0x16900 +#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 +#define ixPB0_RX_LANE7_CTRL_REG0 0x16A00 +#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 +#define ixPB0_RX_LANE8_CTRL_REG0 0x17440 +#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 +#define ixPB0_RX_LANE9_CTRL_REG0 0x17480 +#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 +#define ixPB0_STRAP_GLB_REG0 0x12020 +#define ixPB0_STRAP_PLL_REG0 0x12030 +#define ixPB0_STRAP_RX_REG0 0x12028 +#define ixPB0_STRAP_RX_REG1 0x1202C +#define ixPB0_STRAP_TX_REG0 0x12024 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 +#define ixPB0_TX_GLB_CTRL_REG0 0x18000 +#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004 +#define ixPB0_TX_GLB_OVRD_REG0 0x18030 +#define ixPB0_TX_GLB_OVRD_REG1 0x18034 +#define ixPB0_TX_GLB_OVRD_REG2 0x18038 +#define ixPB0_TX_GLB_OVRD_REG3 0x1803C +#define ixPB0_TX_GLB_OVRD_REG4 0x18040 +#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 +#define ixPB0_TX_LANE0_CTRL_REG0 0x18440 +#define ixPB0_TX_LANE0_OVRD_REG0 0x18444 +#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 +#define ixPB0_TX_LANE10_CTRL_REG0 0x19500 +#define ixPB0_TX_LANE10_OVRD_REG0 0x19504 +#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 +#define ixPB0_TX_LANE11_CTRL_REG0 0x19600 +#define ixPB0_TX_LANE11_OVRD_REG0 0x19604 +#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 +#define ixPB0_TX_LANE12_CTRL_REG0 0x19840 +#define ixPB0_TX_LANE12_OVRD_REG0 0x19844 +#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 +#define ixPB0_TX_LANE13_CTRL_REG0 0x19880 +#define ixPB0_TX_LANE13_OVRD_REG0 0x19884 +#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 +#define ixPB0_TX_LANE14_CTRL_REG0 0x19900 +#define ixPB0_TX_LANE14_OVRD_REG0 0x19904 +#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 +#define ixPB0_TX_LANE15_CTRL_REG0 0x19A00 +#define ixPB0_TX_LANE15_OVRD_REG0 0x19A04 +#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 +#define ixPB0_TX_LANE1_CTRL_REG0 0x18480 +#define ixPB0_TX_LANE1_OVRD_REG0 0x18484 +#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 +#define ixPB0_TX_LANE2_CTRL_REG0 0x18500 +#define ixPB0_TX_LANE2_OVRD_REG0 0x18504 +#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 +#define ixPB0_TX_LANE3_CTRL_REG0 0x18600 +#define ixPB0_TX_LANE3_OVRD_REG0 0x18604 +#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 +#define ixPB0_TX_LANE4_CTRL_REG0 0x18840 +#define ixPB0_TX_LANE4_OVRD_REG0 0x18844 +#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 +#define ixPB0_TX_LANE5_CTRL_REG0 0x18880 +#define ixPB0_TX_LANE5_OVRD_REG0 0x18884 +#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 +#define ixPB0_TX_LANE6_CTRL_REG0 0x18900 +#define ixPB0_TX_LANE6_OVRD_REG0 0x18904 +#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 +#define ixPB0_TX_LANE7_CTRL_REG0 0x18A00 +#define ixPB0_TX_LANE7_OVRD_REG0 0x18A04 +#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 +#define ixPB0_TX_LANE8_CTRL_REG0 0x19440 +#define ixPB0_TX_LANE8_OVRD_REG0 0x19444 +#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 +#define ixPB0_TX_LANE9_CTRL_REG0 0x19480 +#define ixPB0_TX_LANE9_OVRD_REG0 0x19484 +#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 +#define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C +#define ixPB1_DFT_JIT_INJ_REG0 0x13000 +#define ixPB1_DFT_JIT_INJ_REG1 0x13004 +#define ixPB1_DFT_JIT_INJ_REG2 0x13008 +#define ixPB1_GLB_CTRL_REG0 0x10004 +#define ixPB1_GLB_CTRL_REG1 0x10008 +#define ixPB1_GLB_CTRL_REG2 0x1000C +#define ixPB1_GLB_CTRL_REG3 0x10010 +#define