From aa771fbe696a8f9d7884409a271558217be08d32 Mon Sep 17 00:00:00 2001 From: Devin Li Date: Wed, 6 May 2026 10:52:54 +0800 Subject: arm64: dts: cix: Add SCMI performance domains for CPUFreq on Sky1 Add SCMI Protocol 13 (Performance) node under ap_to_pm_scmi with domains. Define SKY1_PERF_* macros in sky1-power.h for all performance domain IDs (CPU L/B0/B1/M0/M1, GPU, DSU, NPU, VPU, CI700, NI700), and wire each CPU node to its corresponding performance domain using power-domains and power-domain-names properties. Signed-off-by: Devin Li Link: https://lore.kernel.org/r/20260506025254.3602623-1-Devin.Li@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1-power.h | 13 +++++++++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-power.h b/arch/arm64/boot/dts/cix/sky1-power.h index 53f4a3af36b3..144567579b71 100644 --- a/arch/arm64/boot/dts/cix/sky1-power.h +++ b/arch/arm64/boot/dts/cix/sky1-power.h @@ -30,4 +30,17 @@ #define SKY1_PD_ISP0 20 #define SKY1_PD_GPU 21 +#define SKY1_PERF_GPU_CORE 0 +#define SKY1_PERF_GPU_TOP 1 +#define SKY1_PERF_CPU_L 2 +#define SKY1_PERF_CPU_B0 3 +#define SKY1_PERF_CPU_B1 4 +#define SKY1_PERF_CPU_M0 5 +#define SKY1_PERF_CPU_M1 6 +#define SKY1_PERF_DSU 7 +#define SKY1_PERF_NPU 8 +#define SKY1_PERF_VPU 9 +#define SKY1_PERF_CI700 10 +#define SKY1_PERF_NI700 11 + #endif diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index bb5cfb1f2113..9f80e1aa070a 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -22,6 +22,8 @@ enable-method = "psci"; reg = <0x0 0x0>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -30,6 +32,8 @@ enable-method = "psci"; reg = <0x0 0x100>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -38,6 +42,8 @@ enable-method = "psci"; reg = <0x0 0x200>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -46,6 +52,8 @@ enable-method = "psci"; reg = <0x0 0x300>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; + power-domain-names = "perf"; capacity-dmips-mhz = <403>; }; @@ -54,6 +62,8 @@ enable-method = "psci"; reg = <0x0 0x400>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -62,6 +72,8 @@ enable-method = "psci"; reg = <0x0 0x500>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -70,6 +82,8 @@ enable-method = "psci"; reg = <0x0 0x600>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -78,6 +92,8 @@ enable-method = "psci"; reg = <0x0 0x700>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -86,6 +102,8 @@ enable-method = "psci"; reg = <0x0 0x800>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -94,6 +112,8 @@ enable-method = "psci"; reg = <0x0 0x900>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -102,6 +122,8 @@ enable-method = "psci"; reg = <0x0 0xa00>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -110,6 +132,8 @@ enable-method = "psci"; reg = <0x0 0xb00>; device_type = "cpu"; + power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; + power-domain-names = "perf"; capacity-dmips-mhz = <1024>; }; @@ -164,6 +188,11 @@ #address-cells = <1>; #size-cells = <0>; + scmi_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; -- cgit v1.2.3 From 89d0ad7f3a60d3076da2d90ece8d78d0eb60bb91 Mon Sep 17 00:00:00 2001 From: Devin Li Date: Thu, 7 May 2026 14:59:56 +0800 Subject: arm64: dts: cix: Add CPU idle states for Sky1 Add PSCI-based CPU idle state definitions for the Sky1 SoC, enabling core and cluster level power management through ARM PSCI firmware. Three idle states are defined: - CPU_SLEEP_0: Core idle state for A520 cores (psci-suspend-param 0x0010000), entry-latency 34us, exit-latency 100us - CPU_SLEEP_1: Core idle state for A720 cores (psci-suspend-param 0x10000), entry-latency 31us, exit-latency 79us - CLUSTER_SLEEP_0: Cluster idle state shared by all cores (psci-suspend-param 0x1010000), entry-latency 41us, exit-latency 104us A520 cores (cpu0-3) reference CPU_SLEEP_0 and CLUSTER_SLEEP_0, while A720 cores (cpu4-11) reference CPU_SLEEP_1 and CLUSTER_SLEEP_0. Signed-off-by: Devin Li Link: https://lore.kernel.org/r/20260507065956.3900087-1-Devin.Li@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 9f80e1aa070a..a77c52296ebd 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -25,6 +25,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@100 { @@ -35,6 +36,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { @@ -45,6 +47,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@300 { @@ -55,6 +58,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; power-domain-names = "perf"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@400 { @@ -65,6 +69,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu5: cpu@500 { @@ -75,6 +80,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu6: cpu@600 { @@ -85,6 +91,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu7: cpu@700 { @@ -95,6 +102,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu8: cpu@800 { @@ -105,6 +113,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu9: cpu@900 { @@ -115,6 +124,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu10: cpu@a00 { @@ -125,6 +135,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu11: cpu@b00 { @@ -135,6 +146,7 @@ power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; power-domain-names = "perf"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu-map { @@ -177,6 +189,35 @@ }; }; }; + + idle-states { + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <34>; + exit-latency-us = <100>; + min-residency-us = <3000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <31>; + exit-latency-us = <79>; + min-residency-us = <3000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <41>; + exit-latency-us = <104>; + min-residency-us = <4000>; + }; + }; }; firmware { -- cgit v1.2.3