From 29df31ae3e8a0152dd8e8c2376816aad2f233473 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 13 Apr 2026 19:24:52 +0100 Subject: pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume Include the SR (Slew Rate) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 38 ++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 1c6b115e65d8..f5f645ba92e0 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -322,6 +322,7 @@ struct rzg2l_pinctrl_pin_settings { * @pupd: PUPD registers cache * @ien: IEN registers cache * @smt: SMT registers cache + * @sr: SR registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache @@ -336,6 +337,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *ien[2]; u32 *pupd[2]; u32 *smt[2]; + u32 *sr[2]; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; @@ -2760,6 +2762,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->smt[i]) return -ENOMEM; + cache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]), + GFP_KERNEL); + if (!cache->sr[i]) + return -ENOMEM; + /* Allocate dedicated cache. */ dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, sizeof(*dedicated_cache->iolh[i]), @@ -2772,6 +2779,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) GFP_KERNEL); if (!dedicated_cache->ien[i]) return -ENOMEM; + + dedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->sr[i]), + GFP_KERNEL); + if (!dedicated_cache->sr[i]) + return -ENOMEM; } pctrl->cache = cache; @@ -3003,7 +3016,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; for (u32 port = 0; port < nports; port++) { - bool has_iolh, has_ien, has_pupd, has_smt; + bool has_iolh, has_ien, has_pupd, has_smt, has_sr; u32 off, caps; u8 pincnt; u64 cfg; @@ -3024,6 +3037,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen has_ien = !!(caps & PIN_CFG_IEN); has_pupd = !!(caps & PIN_CFG_PUPD); has_smt = !!(caps & PIN_CFG_SMT); + has_sr = !!(caps & PIN_CFG_SR); if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); @@ -3075,6 +3089,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen cache->smt[1][port]); } } + + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), + cache->sr[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4, + cache->sr[1][port]); + } + } } } @@ -3089,7 +3112,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b * port offset are close together. */ for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { - bool has_iolh, has_ien; + bool has_iolh, has_ien, has_sr; u32 off, next_off = 0; u64 cfg, next_cfg; u8 pincnt; @@ -3110,6 +3133,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b /* And apply them in a single shot. */ has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); has_ien = !!(caps & PIN_CFG_IEN); + has_sr = !!(caps & PIN_CFG_SR); pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); if (has_iolh) { @@ -3120,7 +3144,10 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), cache->ien[0][i]); } - + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), + cache->sr[0][i]); + } if (pincnt >= 4) { if (has_iolh) { RZG2L_PCTRL_REG_ACCESS32(suspend, @@ -3132,6 +3159,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b pctrl->base + IEN(off) + 4, cache->ien[1][i]); } + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + SR(off) + 4, + cache->sr[1][i]); + } } caps = 0; } -- cgit v1.2.3 From d0fc9f8eb2ce55eb00dbfdc0f19c844df5aee5b8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 13 Apr 2026 19:24:53 +0100 Subject: pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cache Include PIN_CFG_IOLH_RZV2H in the IOLH capability checks when saving and restoring pin configuration registers. On RZ/V2H(P), RZ/V2N, and RZ/G3E, the IOLH configuration is defined by the PIN_CFG_IOLH_RZV2H capability. The previous implementation did not account for this, causing the IOLH registers to be skipped during PM save/restore. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260413182456.811543-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f5f645ba92e0..164429ac20d9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3131,7 +3131,8 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b } /* And apply them in a single shot. */ - has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); + has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | + PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H)); has_ien = !!(caps & PIN_CFG_IEN); has_sr = !!(caps & PIN_CFG_SR); pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); -- cgit v1.2.3 From 25e71db480358c1993f91e69078cb5d9b26cd705 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 13 Apr 2026 19:24:54 +0100 Subject: pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume Include the NOD (N-ch Open Drain) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260413182456.811543-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 37 +++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 164429ac20d9..bcedc79d80da 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -323,6 +323,7 @@ struct rzg2l_pinctrl_pin_settings { * @ien: IEN registers cache * @smt: SMT registers cache * @sr: SR registers cache + * @nod: NOD registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache @@ -338,6 +339,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *pupd[2]; u32 *smt[2]; u32 *sr[2]; + u32 *nod[2]; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; @@ -2767,6 +2769,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->sr[i]) return -ENOMEM; + cache->nod[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->nod[i]), + GFP_KERNEL); + if (!cache->nod[i]) + return -ENOMEM; + /* Allocate dedicated cache. */ dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, sizeof(*dedicated_cache->iolh[i]), @@ -2785,6 +2792,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) GFP_KERNEL); if (!dedicated_cache->sr[i]) return -ENOMEM; + + dedicated_cache->nod[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->nod[i]), + GFP_KERNEL); + if (!dedicated_cache->nod[i]) + return -ENOMEM; } pctrl->cache = cache; @@ -3016,7 +3029,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; for (u32 port = 0; port < nports; port++) { - bool has_iolh, has_ien, has_pupd, has_smt, has_sr; + bool has_iolh, has_ien, has_pupd, has_smt, has_sr, has_nod; u32 off, caps; u8 pincnt; u64 cfg; @@ -3038,6 +3051,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen has_pupd = !!(caps & PIN_CFG_PUPD); has_smt = !!(caps & PIN_CFG_SMT); has_sr = !!(caps & PIN_CFG_SR); + has_nod = !!(caps & PIN_CFG_NOD); if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); @@ -3098,6 +3112,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen cache->sr[1][port]); } } + + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), + cache->nod[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off) + 4, + cache->nod[1][port]); + } + } } } @@ -3112,7 +3135,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b * port offset are close together. */ for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { - bool has_iolh, has_ien, has_sr; + bool has_iolh, has_ien, has_sr, has_nod; u32 off, next_off = 0; u64 cfg, next_cfg; u8 pincnt; @@ -3135,6 +3158,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H)); has_ien = !!(caps & PIN_CFG_IEN); has_sr = !!(caps & PIN_CFG_SR); + has_nod = !!(caps & PIN_CFG_NOD); pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); if (has_iolh) { @@ -3149,6 +3173,10 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), cache->sr[0][i]); } + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), + cache->nod[0][i]); + } if (pincnt >= 4) { if (has_iolh) { RZG2L_PCTRL_REG_ACCESS32(suspend, @@ -3165,6 +3193,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b pctrl->base + SR(off) + 4, cache->sr[1][i]); } + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + NOD(off) + 4, + cache->nod[1][i]); + } } caps = 0; } -- cgit v1.2.3 From eea549769cb7cae28cc3158befa2de1b7e92bf58 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 13 Apr 2026 19:24:55 +0100 Subject: pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM On RZ/V2H(P), dedicated pins support pull-up/pull-down configuration via PIN_CFG_PUPD. Add PUPD handling for dedicated pins in the PM save/restore path. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index bcedc79d80da..bc2154b69514 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2798,6 +2798,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) GFP_KERNEL); if (!dedicated_cache->nod[i]) return -ENOMEM; + + dedicated_cache->pupd[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->pupd[i]), + GFP_KERNEL); + if (!dedicated_cache->pupd[i]) + return -ENOMEM; } pctrl->cache = cache; @@ -3135,7 +3141,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b * port offset are close together. */ for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { - bool has_iolh, has_ien, has_sr, has_nod; + bool has_iolh, has_ien, has_sr, has_nod, has_pupd; u32 off, next_off = 0; u64 cfg, next_cfg; u8 pincnt; @@ -3159,6 +3165,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b has_ien = !!(caps & PIN_CFG_IEN); has_sr = !!(caps & PIN_CFG_SR); has_nod = !!(caps & PIN_CFG_NOD); + has_pupd = !!(caps & PIN_CFG_PUPD); pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); if (has_iolh) { @@ -3177,6 +3184,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), cache->nod[0][i]); } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + cache->pupd[0][i]); + } + if (pincnt >= 4) { if (has_iolh) { RZG2L_PCTRL_REG_ACCESS32(suspend, @@ -3198,6 +3210,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b pctrl->base + NOD(off) + 4, cache->nod[1][i]); } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + PUPD(off) + 4, + cache->pupd[1][i]); + } } caps = 0; } -- cgit v1.2.3 From 38eec41ded8621c75e5772af5fccde906fcd8276 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 12:30:06 +0200 Subject: pinctrl: tegra: Enable easier compile testing Currently NVIDIA Tegra pin controller drivers cannot be compile tested, unless ARCH_TEGRA is selected. That partially defeats the purpose of compile testing, since ARCH_TEGRA is pulled when building platform kernels. Solve it and allow compile testing independently of ARCH_TEGRA choice which requires few less usual changes: 1. Descent in Makefile in to drivers/pinctrl/tegra/ unconditionally, because there is no menu option. 2. Depend on COMMON_CLK for PINCTRL_TEGRA20, because it uses clk_register_mux(). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/tegra/Kconfig | 22 ++++++++++++---------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f7d5d5f76d0c..9d33fa28a096 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -93,7 +93,7 @@ obj-y += starfive/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-y += sunplus/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ -obj-$(CONFIG_ARCH_TEGRA) += tegra/ +obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig index 660d101ea367..3e8789871f0f 100644 --- a/drivers/pinctrl/tegra/Kconfig +++ b/drivers/pinctrl/tegra/Kconfig @@ -1,43 +1,45 @@ # SPDX-License-Identifier: GPL-2.0-only config PINCTRL_TEGRA - bool + bool "NVIDIA Tegra pin controllers common" if COMPILE_TEST && !ARCH_TEGRA select PINMUX select PINCONF config PINCTRL_TEGRA20 - bool + bool "NVIDIA Tegra20 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA + depends on COMMON_CLK config PINCTRL_TEGRA30 - bool + bool "NVIDIA Tegra30 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA114 - bool + bool "NVIDIA Tegra114 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA124 - bool + bool "NVIDIA Tegra124 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA210 - bool + bool "NVIDIA Tegra210 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA186 - bool + bool "NVIDIA Tegra186 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA194 - bool + bool "NVIDIA Tegra194 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA234 - bool + bool "NVIDIA Tegra234 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA_XUSB - def_bool y if ARCH_TEGRA + bool "NVIDIA Tegra XUSB pin controller" if COMPILE_TEST && !ARCH_TEGRA + default y if ARCH_TEGRA select GENERIC_PHY select PINCONF select PINMUX -- cgit v1.2.3 From 32ba46cede2807215d6c503f27cf554226ecaa9f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 15:04:56 +0200 Subject: pinctrl: realtek: Enable compile testing Enable compile testing for Realtek pin controller drivers for increased build and static checkers coverage. PINCTRL_RTD uses pinconf_generic_dt_node_to_map(), thus needs OF. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/realtek/Kconfig | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9d33fa28a096..b054cfb99348 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -82,7 +82,7 @@ obj-y += nuvoton/ obj-y += nxp/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-y += qcom/ -obj-$(CONFIG_ARCH_REALTEK) += realtek/ +obj-$(CONFIG_PINCTRL_RTD) += realtek/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-y += sophgo/ diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig index 054e85db99e7..a156c4ef556e 100644 --- a/drivers/pinctrl/realtek/Kconfig +++ b/drivers/pinctrl/realtek/Kconfig @@ -2,8 +2,8 @@ config PINCTRL_RTD tristate "Realtek DHC core pin controller driver" - depends on ARCH_REALTEK - default y + depends on ARCH_REALTEK || (COMPILE_TEST && OF) + default ARCH_REALTEK select PINMUX select GENERIC_PINCONF select REGMAP_MMIO @@ -11,22 +11,22 @@ config PINCTRL_RTD config PINCTRL_RTD1619B tristate "Realtek DHC 1619B pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK config PINCTRL_RTD1319D tristate "Realtek DHC 1319D pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK config PINCTRL_RTD1315E tristate "Realtek DHC 1315E pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK config PINCTRL_RTD1625 tristate "Realtek DHC 1625 pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK help This driver enables support for the pin controller on the Realtek RTD1625 SoCs. -- cgit v1.2.3 From 0e6ba181b7982bd82a92698d2c8eec621d4eef9d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 15:04:57 +0200 Subject: pinctrl: aspeed: Enable compile testing outside of ARCH_ASPEED Since inception in commit 4d3d0e4272d8 ("pinctrl: Add core support for Aspeed SoCs"), the Aspeed pin controller drivers cannot be compile tested, unless ARCH_ASPEED is selected. . That partially defeats the purpose of compile testing, since ARCH_ASPEED is pulled when building platform kernels. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index b054cfb99348..9320ffae5f31 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -66,7 +66,7 @@ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-y += actions/ -obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_PINCTRL_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += cirrus/ -- cgit v1.2.3 From 93d8c6c0e1879d098ff478511032b42a6b26aae0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 15:04:58 +0200 Subject: pinctrl: vt8500: Enable compile testing Enable compile testing for Realtek pin controller drivers for increased build and static checkers coverage. PINCTRL_WMT uses gpiochip_get_data(), thus needs GPIOLIB. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/vt8500/Kconfig | 13 +++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9320ffae5f31..78135ee963db 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -97,4 +97,4 @@ obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ -obj-$(CONFIG_ARCH_VT8500) += vt8500/ +obj-$(CONFIG_PINCTRL_WMT) += vt8500/ diff --git a/drivers/pinctrl/vt8500/Kconfig b/drivers/pinctrl/vt8500/Kconfig index 2ca00b54b7a8..1a40c153a82a 100644 --- a/drivers/pinctrl/vt8500/Kconfig +++ b/drivers/pinctrl/vt8500/Kconfig @@ -3,16 +3,17 @@ # VIA/Wondermedia PINCTRL drivers # -if ARCH_VT8500 +if ARCH_VT8500 || COMPILE_TEST config PINCTRL_WMT bool select PINMUX select GENERIC_PINCONF + select GPIOLIB config PINCTRL_VT8500 bool "VIA VT8500 pin controller driver" - depends on ARCH_WM8505 + depends on ARCH_WM8505 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -20,7 +21,7 @@ config PINCTRL_VT8500 config PINCTRL_WM8505 bool "Wondermedia WM8505 pin controller driver" - depends on ARCH_WM8505 + depends on ARCH_WM8505 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -28,7 +29,7 @@ config PINCTRL_WM8505 config PINCTRL_WM8650 bool "Wondermedia WM8650 pin controller driver" - depends on ARCH_WM8505 + depends on ARCH_WM8505 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -36,7 +37,7 @@ config PINCTRL_WM8650 config PINCTRL_WM8750 bool "Wondermedia WM8750 pin controller driver" - depends on ARCH_WM8750 + depends on ARCH_WM8750 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -44,7 +45,7 @@ config PINCTRL_WM8750 config PINCTRL_WM8850 bool "Wondermedia WM8850 pin controller driver" - depends on ARCH_WM8850 + depends on ARCH_WM8850 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on -- cgit v1.2.3 From 61b5deb5a968f7a82124f9b2591a6a151ed7273a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 13:10:48 +0200 Subject: dt-bindings: pinctrl: nvidia,tegra234: Add missing required block Binding should require 'reg' property, because address space cannot be missing in the hardware and is already needed by the Linux drivers. Require also 'compatible' by convention, although it is not strictly necessary. Fixes: 857982138b79 ("dt-bindings: pinctrl: Document Tegra234 pin controllers") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml | 4 ++++ Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index db8224dfba2c..56fb9cf763ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -58,6 +58,10 @@ patternProperties: drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] +required: + - compatible + - reg + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml index f5a3a881dec4..bd305a34eee2 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -115,6 +115,10 @@ patternProperties: drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, drive_sdmmc1_dat0_pj2 ] +required: + - compatible + - reg + unevaluatedProperties: false examples: -- cgit v1.2.3 From 39dcfa63dc479c97ba90170b972116030a4e184d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 13:10:49 +0200 Subject: dt-bindings: pinctrl: nvidia,tegra234: Correctly use additionalProperties The binding does not reference any other schema, thus should use "additionalProperties: false" to disallow any undocumented properties. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml | 2 +- Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index 56fb9cf763ef..4910dc8e8aeb 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -62,7 +62,7 @@ required: - compatible - reg -unevaluatedProperties: false +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml index bd305a34eee2..52b3d40e8839 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -119,7 +119,7 @@ required: - compatible - reg -unevaluatedProperties: false +additionalProperties: false examples: - | -- cgit v1.2.3 From 58631a03cf647ea93c2060d87d45f0c019fbfbbc Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Wed, 15 Apr 2026 16:59:24 +0530 Subject: dt-bindings: pinctrl: qcom: add IPQ9650 pinctrl Add device tree bindings for IPQ9650 TLMM block. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,ipq9650-tlmm.yaml | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml new file mode 100644 index 000000000000..549eaa6aa11b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ9650 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq9650-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq9650-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq9650-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq9650-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, + audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1, + audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0, + audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1, + core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3, + core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, + mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0, + mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n, + pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n, + pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync, + pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data, + qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3, + qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1, + rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9650-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart1-default-state { + pins = "gpio43", "gpio44"; + function = "qup_se6"; + drive-strength = <8>; + bias-pull-down; + }; + }; -- cgit v1.2.3 From 3c8e7ba0e3996723f7e4be7c982826a9c2be828b Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Wed, 15 Apr 2026 16:59:25 +0530 Subject: pinctrl: qcom: Introduce IPQ9650 TLMM driver Qualcomm's IPQ9650 comes with a TLMM block, like all other platforms, so add a driver for it. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig.msm | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq9650.c | 762 +++++++++++++++++++++++++++++++++ 3 files changed, 772 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9650.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 836cdeca1006..0d6f698e26ec 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -120,6 +120,15 @@ config PINCTRL_IPQ9574 Qualcomm Technologies Inc. IPQ9574 platform. Select this for IPQ9574. +config PINCTRL_IPQ9650 + tristate "Qualcomm Technologies, Inc. IPQ9650 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ9650 platform. Select this for + IPQ9650. + config PINCTRL_KAANAPALI tristate "Qualcomm Technologies Inc Kaanapali pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 84bda3ada874..f0bb1920b27b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o +obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9650.c b/drivers/pinctrl/qcom/pinctrl-ipq9650.c new file mode 100644 index 000000000000..64e443aa31b2 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq9650.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs = 10, \ + } + +static const struct pinctrl_pin_desc ipq9650_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); + +enum ipq9650_functions { + msm_mux_atest_char_start, + msm_mux_atest_char_status0, + msm_mux_atest_char_status1, + msm_mux_atest_char_status2, + msm_mux_atest_char_status3, + msm_mux_atest_tic_en, + msm_mux_audio_pri_mclk_in0, + msm_mux_audio_pri_mclk_out0, + msm_mux_audio_pri_mclk_in1, + msm_mux_audio_pri_mclk_out1, + msm_mux_audio_pri, + msm_mux_audio_sec, + msm_mux_audio_sec_mclk_in0, + msm_mux_audio_sec_mclk_out0, + msm_mux_audio_sec_mclk_in1, + msm_mux_audio_sec_mclk_out1, + msm_mux_core_voltage_0, + msm_mux_core_voltage_1, + msm_mux_core_voltage_2, + msm_mux_core_voltage_3, + msm_mux_core_voltage_4, + msm_mux_cri_rng0, + msm_mux_cri_rng1, + msm_mux_cri_rng2, + msm_mux_dbg_out_clk, + msm_mux_gcc_plltest_bypassnl, + msm_mux_gcc_plltest_resetn, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_mdc_mst, + msm_mux_mdc_slv0, + msm_mux_mdc_slv1, + msm_mux_mdio_mst, + msm_mux_mdio_slv, + msm_mux_mdio_slv0, + msm_mux_mdio_slv1, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk_req_n, + msm_mux_pcie3_wake, + msm_mux_pcie4_clk_req_n, + msm_mux_pcie4_wake, + msm_mux_pll_bist_sync, + msm_mux_pll_test, + msm_mux_pwm, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs_n, + msm_mux_qup_se0, + msm_mux_qup_se1, + msm_mux_qup_se2, + msm_mux_qup_se3, + msm_mux_qup_se4, + msm_mux_qup_se5, + msm_mux_qup_se6, + msm_mux_qup_se7, + msm_mux_resout, + msm_mux_rx_los0, + msm_mux_rx_los1, + msm_mux_rx_los2, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_tsens_max, + msm_mux_tsn, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char *const atest_char_start_groups[] = { + "gpio21", +}; + +static const char *const atest_char_status0_groups[] = { + "gpio33", +}; + +static const char *const atest_char_status1_groups[] = { + "gpio35", +}; + +static const char *const atest_char_status2_groups[] = { + "gpio22", +}; + +static const char *const atest_char_status3_groups[] = { + "gpio23", +}; + +static const char *const atest_tic_en_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_in0_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_out0_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_in1_groups[] = { + "gpio51", +}; + +static const char *const audio_pri_mclk_out1_groups[] = { + "gpio51", +}; + +static const char *const audio_pri_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const audio_sec_mclk_in0_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_out0_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_in1_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_out1_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const core_voltage_0_groups[] = { + "gpio16", +}; + +static const char *const core_voltage_1_groups[] = { + "gpio17", +}; + +static const char *const core_voltage_2_groups[] = { + "gpio33", +}; + +static const char *const core_voltage_3_groups[] = { + "gpio34", +}; + +static const char *const core_voltage_4_groups[] = { + "gpio35", +}; + +static const char *const cri_rng0_groups[] = { + "gpio6", +}; + +static const char *const cri_rng1_groups[] = { + "gpio7", +}; + +static const char *const cri_rng2_groups[] = { + "gpio8", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio46", +}; + +static const char *const gcc_plltest_bypassnl_groups[] = { + "gpio33", +}; + +static const char *const gcc_plltest_resetn_groups[] = { + "gpio35", +}; + +static const char *const gcc_tlmm_groups[] = { + "gpio34", +}; + +static const char *const mdc_mst_groups[] = { + "gpio22", +}; + +static const char *const mdc_slv0_groups[] = { + "gpio20", +}; + +static const char *const mdc_slv1_groups[] = { + "gpio14", +}; + +static const char *const mdio_mst_groups[] = { + "gpio23", +}; + +static const char *const mdio_slv_groups[] = { + "gpio46", + "gpio47", +}; + +static const char *const mdio_slv0_groups[] = { + "gpio21", +}; + +static const char *const mdio_slv1_groups[] = { + "gpio15", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio24", +}; + +static const char *const pcie0_wake_groups[] = { + "gpio26", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio27", +}; + +static const char *const pcie1_wake_groups[] = { + "gpio29", +}; + +static const char *const pcie2_clk_req_n_groups[] = { + "gpio51", +}; + +static const char *const pcie2_wake_groups[] = { + "gpio53", +}; + +static const char *const pcie3_clk_req_n_groups[] = { + "gpio40", +}; + +static const char *const pcie3_wake_groups[] = { + "gpio42", +}; + +static const char *const pcie4_clk_req_n_groups[] = { + "gpio30", +}; + +static const char *const pcie4_wake_groups[] = { + "gpio32", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio47", +}; + +static const char *const pll_test_groups[] = { + "gpio39", +}; + +static const char *const pwm_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", + "gpio17", "gpio33", "gpio34", "gpio35", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", +}; + +static const char *const qdss_cti_trig_in_a0_groups[] = { + "gpio53", +}; + +static const char *const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char *const qdss_cti_trig_in_b0_groups[] = { + "gpio42", +}; + +static const char *const qdss_cti_trig_in_b1_groups[] = { + "gpio43", +}; + +static const char *const qdss_cti_trig_out_a0_groups[] = { + "gpio51", +}; + +static const char *const qdss_cti_trig_out_a1_groups[] = { + "gpio27", +}; + +static const char *const qdss_cti_trig_out_b0_groups[] = { + "gpio40", +}; + +static const char *const qdss_cti_trig_out_b1_groups[] = { + "gpio44", +}; + +static const char *const qdss_traceclk_a_groups[] = { + "gpio45", +}; + +static const char *const qdss_tracectl_a_groups[] = { + "gpio46", +}; + +static const char *const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qspi_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qspi_clk_groups[] = { + "gpio5", +}; + +static const char *const qspi_cs_n_groups[] = { + "gpio4", +}; + +static const char *const qup_se0_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio51", "gpio53", +}; + +static const char *const qup_se1_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio27", "gpio29", +}; + +static const char *const qup_se2_groups[] = { + "gpio27", "gpio29", "gpio33", "gpio34", +}; + +static const char *const qup_se3_groups[] = { + "gpio16", "gpio17", "gpio20", "gpio21", +}; + +static const char *const qup_se4_groups[] = { + "gpio14", "gpio15", "gpio40", "gpio42", "gpio43", "gpio44", +}; + +static const char *const qup_se5_groups[] = { + "gpio40", "gpio42", "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const qup_se6_groups[] = { + "gpio43", "gpio44", "gpio51", "gpio53", +}; + +static const char *const qup_se7_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const resout_groups[] = { + "gpio49", +}; + +static const char *const rx_los0_groups[] = { + "gpio39", "gpio47", "gpio50", +}; + +static const char *const rx_los1_groups[] = { + "gpio38", "gpio46", +}; + +static const char *const rx_los2_groups[] = { + "gpio37", "gpio45", +}; + +static const char *const sdc_clk_groups[] = { + "gpio5", +}; + +static const char *const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char *const sdc_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const tsens_max_groups[] = { + "gpio14", +}; + +static const char *const tsn_groups[] = { + "gpio50", +}; + +static const struct pinfunction ipq9650_functions[] = { + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_char_status0), + MSM_PIN_FUNCTION(atest_char_status1), + MSM_PIN_FUNCTION(atest_char_status2), + MSM_PIN_FUNCTION(atest_char_status3), + MSM_PIN_FUNCTION(atest_tic_en), + MSM_PIN_FUNCTION(audio_pri_mclk_in0), + MSM_PIN_FUNCTION(audio_pri_mclk_out0), + MSM_PIN_FUNCTION(audio_pri_mclk_in1), + MSM_PIN_FUNCTION(audio_pri_mclk_out1), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec_mclk_in0), + MSM_PIN_FUNCTION(audio_sec_mclk_out0), + MSM_PIN_FUNCTION(audio_sec_mclk_in1), + MSM_PIN_FUNCTION(audio_sec_mclk_out1), + MSM_PIN_FUNCTION(core_voltage_0), + MSM_PIN_FUNCTION(core_voltage_1), + MSM_PIN_FUNCTION(core_voltage_2), + MSM_PIN_FUNCTION(core_voltage_3), + MSM_PIN_FUNCTION(core_voltage_4), + MSM_PIN_FUNCTION(cri_rng0), + MSM_PIN_FUNCTION(cri_rng1), + MSM_PIN_FUNCTION(cri_rng2), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(gcc_plltest_bypassnl), + MSM_PIN_FUNCTION(gcc_plltest_resetn), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv0), + MSM_PIN_FUNCTION(mdc_slv1), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv), + MSM_PIN_FUNCTION(mdio_slv0), + MSM_PIN_FUNCTION(mdio_slv1), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(pcie4_clk_req_n), + MSM_PIN_FUNCTION(pcie4_wake), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs_n), + MSM_PIN_FUNCTION(qup_se0), + MSM_PIN_FUNCTION(qup_se1), + MSM_PIN_FUNCTION(qup_se2), + MSM_PIN_FUNCTION(qup_se3), + MSM_PIN_FUNCTION(qup_se4), + MSM_PIN_FUNCTION(qup_se5), + MSM_PIN_FUNCTION(qup_se6), + MSM_PIN_FUNCTION(qup_se7), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx_los0), + MSM_PIN_FUNCTION(rx_los1), + MSM_PIN_FUNCTION(rx_los2), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(tsn), +}; + +static const struct msm_pingroup ipq9650_groups[] = { + [0] = PINGROUP(0, sdc_data, qspi_data, _, _, _, _, _, _, _), + [1] = PINGROUP(1, sdc_data, qspi_data, _, _, _, _, _, _, _), + [2] = PINGROUP(2, sdc_data, qspi_data, _, _, _, _, _, _, _), + [3] = PINGROUP(3, sdc_data, qspi_data, _, _, _, _, _, _, _), + [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), + [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup_se0, pwm, _, cri_rng0, qdss_tracedata_a, _, _, _, _), + [7] = PINGROUP(7, qup_se0, pwm, _, cri_rng1, qdss_tracedata_a, _, _, _, _), + [8] = PINGROUP(8, qup_se0, pwm, _, cri_rng2, qdss_tracedata_a, _, _, _, _), + [9] = PINGROUP(9, qup_se0, pwm, _, qdss_tracedata_a, _, _, _, _, _), + [10] = PINGROUP(10, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _), + [11] = PINGROUP(11, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _), + [12] = PINGROUP(12, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _), + [13] = PINGROUP(13, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _), + [14] = PINGROUP(14, qup_se4, mdc_slv1, tsens_max, _, qdss_tracedata_a, _, _, _, _), + [15] = PINGROUP(15, qup_se4, mdio_slv1, _, qdss_tracedata_a, _, _, _, _, _), + [16] = PINGROUP(16, core_voltage_0, qup_se3, pwm, _, _, _, _, _, _), + [17] = PINGROUP(17, core_voltage_1, qup_se3, pwm, _, _, _, _, _, _), + [18] = PINGROUP(18, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, mdc_slv0, qup_se3, _, qdss_tracedata_a, _, _, _, _, _), + [21] = PINGROUP(21, mdio_slv0, qup_se3, atest_char_start, _, qdss_tracedata_a, _, _, _, _), + [22] = PINGROUP(22, mdc_mst, atest_char_status2, _, _, _, _, _, _, _), + [23] = PINGROUP(23, mdio_mst, atest_char_status3, _, _, _, _, _, _, _), + [24] = PINGROUP(24, pcie0_clk_req_n, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, pcie0_wake, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, pcie1_clk_req_n, qup_se2, qup_se1, _, qdss_cti_trig_out_a1, _, _, _, _), + [28] = PINGROUP(28, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, pcie1_wake, qup_se2, qup_se1, _, qdss_cti_trig_in_a1, _, _, _, _), + [30] = PINGROUP(30, pcie4_clk_req_n, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, pcie4_wake, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, core_voltage_2, qup_se2, gcc_plltest_bypassnl, pwm, atest_char_status0, _, _, _, _), + [34] = PINGROUP(34, core_voltage_3, qup_se2, gcc_tlmm, pwm, _, _, _, _, _), + [35] = PINGROUP(35, core_voltage_4, gcc_plltest_resetn, pwm, atest_char_status1, _, _, _, _, _), + [36] = PINGROUP(36, audio_pri, qup_se7, qdss_tracedata_a, _, _, _, _, _, _), + [37] = PINGROUP(37, audio_pri, qup_se7, audio_sec_mclk_out0, audio_sec_mclk_in0, rx_los2, qdss_tracedata_a, _, _, _), + [38] = PINGROUP(38, audio_pri, qup_se7, rx_los1, qdss_tracedata_a, _, _, _, _, _), + [39] = PINGROUP(39, audio_pri, qup_se7, audio_sec_mclk_out1, audio_sec_mclk_in1, pll_test, rx_los0, _, qdss_tracedata_a, _), + [40] = PINGROUP(40, pcie3_clk_req_n, qup_se5, qup_se4, _, qdss_cti_trig_out_b0, _, _, _, _), + [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, pcie3_wake, qup_se5, qup_se4, _, qdss_cti_trig_in_b0, _, _, _, _), + [43] = PINGROUP(43, qup_se4, qup_se6, pwm, _, qdss_cti_trig_in_b1, _, _, _, _), + [44] = PINGROUP(44, qup_se4, qup_se6, pwm, _, qdss_cti_trig_out_b1, _, _, _, _), + [45] = PINGROUP(45, qup_se5, rx_los2, audio_sec, pwm, _, qdss_traceclk_a, _, _, _), + [46] = PINGROUP(46, qup_se5, rx_los1, audio_sec, mdio_slv, pwm, dbg_out_clk, qdss_tracectl_a, _, _), + [47] = PINGROUP(47, qup_se5, rx_los0, audio_sec, mdio_slv, pll_bist_sync, pwm, _, _, _), + [48] = PINGROUP(48, qup_se5, audio_sec, pwm, _, _, _, _, _, _), + [49] = PINGROUP(49, resout, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, tsn, rx_los0, _, _, _, _, _, _, _), + [51] = PINGROUP(51, pcie2_clk_req_n, qup_se6, qup_se0, audio_pri_mclk_out1, audio_pri_mclk_in1, qdss_cti_trig_out_a0, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, pcie2_wake, qup_se6, qup_se0, audio_pri_mclk_out0, audio_pri_mclk_in0, qdss_cti_trig_in_a0, _, atest_tic_en, _), +}; + +static const struct msm_pinctrl_soc_data ipq9650_tlmm = { + .pins = ipq9650_pins, + .npins = ARRAY_SIZE(ipq9650_pins), + .functions = ipq9650_functions, + .nfunctions = ARRAY_SIZE(ipq9650_functions), + .groups = ipq9650_groups, + .ngroups = ARRAY_SIZE(ipq9650_groups), + .ngpios = 54, +}; + +static const struct of_device_id ipq9650_tlmm_of_match[] = { + { .compatible = "qcom,ipq9650-tlmm", }, + {}, +}; + +static int ipq9650_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq9650_tlmm); +} + +static struct platform_driver ipq9650_tlmm_driver = { + .driver = { + .name = "ipq9650-tlmm", + .of_match_table = ipq9650_tlmm_of_match, + }, + .probe = ipq9650_tlmm_probe, +}; + +static int __init ipq9650_tlmm_init(void) +{ + return platform_driver_register(&ipq9650_tlmm_driver); +} +arch_initcall(ipq9650_tlmm_init); + +static void __exit ipq9650_tlmm_exit(void) +{ + platform_driver_unregister(&ipq9650_tlmm_driver); +} +module_exit(ipq9650_tlmm_exit); + +MODULE_DESCRIPTION("QTI IPQ9650 TLMM driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 728bf8ecac7733848a214b95b1aba41e0ee3ffb9 Mon Sep 17 00:00:00 2001 From: Yash Suthar Date: Sun, 19 Apr 2026 00:41:24 +0530 Subject: pinctrl: pinconf-generic: Use kmemdup_array() over kmemdup() using kmemdup_array instead of kmemdup ,as it is more readable and matches the intent of the api. tested with w=1, no new warnings introduced. Signed-off-by: Yash Suthar Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 64ed28309788..d333ddd44298 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -419,7 +419,7 @@ int pinconf_generic_parse_dt_config(struct device_node *np, * Now limit the number of configs to the real number of * found properties. */ - *configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL); + *configs = kmemdup_array(cfg, ncfg, sizeof(unsigned long), GFP_KERNEL); if (!*configs) { ret = -ENOMEM; goto out; -- cgit v1.2.3 From 5502ca2ae63ce02f1c1ce03aea3135d606e91060 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Thu, 23 Apr 2026 04:43:19 +0000 Subject: dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates Several QUP lanes have MIRA/MIRB mirror routings that let the same lane be muxed out on alternative GPIOs. On Eliza these were all collapsed under the base function name (e.g. qup1_se6), which prevented boards from selecting the mirror variants. Add explicit function names for each mirror lane, matching the pattern already established by qcom,sm8550-tlmm and related bindings. Signed-off-by: Alexander Koskovich Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,eliza-tlmm.yaml | 25 +++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index 282650426487..be7b4680045f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -86,16 +86,21 @@ $defs: qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, qlink_big_request, qlink_little_enable, qlink_little_request, qlink_wmss, qspi0, qspi_clk, - qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, - qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, - qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, - qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, - sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, - tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, - tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, - uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, - uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, - vsense_trigger_mirnat, wcn_sw_ctrl ] + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, + qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, + qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, + qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, + qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb, + qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5, + qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1, + sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ] required: - pins -- cgit v1.2.3 From 1bd5c56253c534840382d01f80e6a6a40ff01dd6 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Thu, 23 Apr 2026 04:43:27 +0000 Subject: dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the function name cannot be the same or the alternate function cannot be selected. Split them up into individual lane functions so boards can specify. Signed-off-by: Alexander Koskovich Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index be7b4680045f..fa0177529277 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -88,7 +88,8 @@ $defs: qlink_little_request, qlink_wmss, qspi0, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, - qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, + qup1_se4_l3, qup1_se5, qup1_se6, qup1_se6_l1_mira, qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, -- cgit v1.2.3 From cef1554c4f7dff8ac3a542b89c2c83afdf734d23 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Thu, 23 Apr 2026 04:43:37 +0000 Subject: pinctrl: qcom: eliza: Split QUP lane mirror alternates Several QUP lanes have MIRA/MIRB mirror routings which are collapsed under a single function name (e.g. qup1_se6). This is an issue because it means there are multiple functions defined for a given pin that share the same name: [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6... So when you select pin 42 and request function qup1_se6, it will select the first instance of it in this group, which just happens to be QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively unreachable. Split each of these lanes that has an alternative GPIO into their own function so they can actually be selected, following the pattern seen in pinctrl-sm8550.c. Signed-off-by: Alexander Koskovich Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-eliza.c | 132 ++++++++++++++++++++++++++++++----- 1 file changed, 114 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c index c1f756cbcdeb..8f74756771b8 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -563,15 +563,31 @@ enum eliza_functions { msm_mux_qup1_se0, msm_mux_qup1_se1, msm_mux_qup1_se2, + msm_mux_qup1