From 28552c2eae472a0a52d1cdb02eb32766c7f690e1 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@deeprootsystems.com>
Date: Thu, 25 Feb 2010 15:36:38 -0800
Subject: davinci: misc cleanups from sparse

- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups:  struct foo *__iomem f --> struct foo __iomem *f;

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/board-dm644x-evm.c  |  2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c |  2 +-
 arch/arm/mach-davinci/board-sffsdr.c      |  2 +-
 arch/arm/mach-davinci/cdce949.c           |  1 +
 arch/arm/mach-davinci/clock.c             |  1 +
 arch/arm/mach-davinci/devices.c           |  2 ++
 arch/arm/mach-davinci/dm355.c             |  2 +-
 arch/arm/mach-davinci/dm365.c             |  2 +-
 arch/arm/mach-davinci/dm644x.c            |  4 ++--
 arch/arm/mach-davinci/dm646x.c            |  6 +++---
 arch/arm/mach-davinci/gpio.c              | 24 ++++++++++++------------
 arch/arm/mach-davinci/include/mach/gpio.h |  8 ++++----
 arch/arm/mach-davinci/mux.c               |  1 +
 13 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 976e11b7fa4a..95cef1f46ef2 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -111,7 +111,7 @@ static struct platform_device davinci_evm_norflash_device = {
  * It may used instead of the (default) NOR chip to boot, using TI's
  * tools to install the secondary boot loader (UBL) and U-Boot.
  */
-struct mtd_partition davinci_evm_nandflash_partition[] = {
+static struct mtd_partition davinci_evm_nandflash_partition[] = {
 	/* Bootloader layout depends on whose u-boot is installed, but we
 	 * can hide all the details.
 	 *  - block 0 for u-boot environment ... in mainline u-boot
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index bd9ca079b69d..1fadc68d9fbb 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -60,7 +60,7 @@
 
 #define NAND_BLOCK_SIZE		SZ_128K
 
-struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
+static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
 	{
 		/* UBL (a few copies) plus U-Boot */
 		.name		= "bootloader",
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 08d373bfcc8a..a7cf810bb13e 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -48,7 +48,7 @@
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
 
-struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
 	/* U-Boot Environment: Block 0
 	 * UBL:                Block 1
 	 * U-Boot:             Blocks 6-7 (256 kb)
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index aec375690543..ba8b12b2913b 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,6 +19,7 @@
 #include <linux/i2c.h>
 
 #include <mach/clock.h>
+#include <mach/cdce949.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index bf6218ee94e1..058c77f72a07 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -22,6 +22,7 @@
 
 #include <mach/hardware.h>
 
+#include <mach/clock.h>
 #include <mach/psc.h>
 #include <mach/cputype.h>
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 147949650c25..ef28080b1fda 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,6 +23,8 @@
 #include <mach/mmc.h>
 #include <mach/time.h>
 
+#include "clock.h"
+
 #define DAVINCI_I2C_BASE	     0x01C21000
 #define DAVINCI_MMCSD0_BASE	     0x01E10000
 #define DM355_MMCSD0_BASE	     0x01E11000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3dc0a88712eb..5efce70ccdd0 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -798,7 +798,7 @@ static void __iomem *dm355_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm355_timer_info = {
+static struct davinci_timer_info dm355_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0d6ee583f65c..871be5af2735 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1010,7 +1010,7 @@ static void __iomem *dm365_psc_bases[] = {
 	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 };
 
-struct davinci_timer_info dm365_timer_info = {
+static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 2f2ae8bc77bb..23cbe9d04bc5 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
 	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
 };
 
-struct clk_lookup dm644x_clks[] = {
+static struct clk_lookup dm644x_clks[] = {
 	CLK(NULL, "ref", &ref_clk),
 	CLK(NULL, "pll1", &pll1_clk),
 	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -687,7 +687,7 @@ static void __iomem *dm644x_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm644x_timer_info = {
+static struct davinci_timer_info dm644x_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 893baf4ad37d..b67b997d0bbc 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
 	.flags = ALWAYS_ENABLED,
 };
 
-struct clk_lookup dm646x_clks[] = {
+static struct clk_lookup dm646x_clks[] = {
 	CLK(NULL, "ref", &ref_clk),
 	CLK(NULL, "aux", &aux_clkin),
 	CLK(NULL, "pll1", &pll1_clk),
@@ -797,7 +797,7 @@ static void __iomem *dm646x_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm646x_timer_info = {
+static struct davinci_timer_info dm646x_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
@@ -867,7 +867,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.sram_len		= SZ_32K,
 };
 
-void __init dm646x_init_ide()
+void __init dm646x_init_ide(void)
 {
 	davinci_cfg_reg(DM646X_ATAEN);
 	platform_device_register(&ide_dev);
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 744755b53236..3f7706266ca6 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -24,14 +24,14 @@ static DEFINE_SPINLOCK(gpio_lock);
 
 struct davinci_gpio {
 	struct gpio_chip	chip;
-	struct gpio_controller	*__iomem regs;
+	struct gpio_controller	__iomem *regs;
 	int			irq_base;
 };
 
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
-static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
+static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
 {
 	return __gpio_to_controller(gpio);
 }
@@ -48,7 +48,7 @@ static int __init davinci_gpio_irq_setup(void);
 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
 
 	spin_lock(&gpio_lock);
@@ -70,7 +70,7 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
@@ -79,7 +79,7 @@ static int
 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
 	u32 mask = 1 << offset;
 
@@ -99,7 +99,7 @@ static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 }
@@ -161,7 +161,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -170,7 +170,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -186,7 +186,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +215,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -276,7 +276,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -305,7 +305,7 @@ static int __init davinci_gpio_irq_setup(void)
 	u32		binten = 0;
 	unsigned	ngpio, bank_irq;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct gpio_controller	*__iomem g;
+	struct gpio_controller	__iomem *g;
 
 	ngpio = soc_info->gpio_num;
 
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f3b8ef878158..0099e6e5aff8 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -67,10 +67,10 @@ struct gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct gpio_controller *__iomem
+static inline struct gpio_controller __iomem *
 __gpio_to_controller(unsigned gpio)
 {
-	void *__iomem ptr;
+	void __iomem *ptr;
 	void __iomem *base = davinci_soc_info.gpio_base;
 
 	if (gpio < 32 * 1)
@@ -102,7 +102,7 @@ static inline u32 __gpio_mask(unsigned gpio)
 static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct gpio_controller	*__iomem g;
+		struct gpio_controller	__iomem *g;
 		u32			mask;
 
 		g = __gpio_to_controller(gpio);
@@ -128,7 +128,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct gpio_controller	*__iomem g;
+	struct gpio_controller	__iomem *g;
 
 	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
 		return __gpio_get_value(gpio);
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f757e83415f3..c942c893a2eb 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,6 +21,7 @@
 
 #include <mach/mux.h>
 #include <mach/common.h>
+#include <mach/da8xx.h>
 
 /*
  * Sets the DAVINCI MUX register based on the table
-- 
cgit v1.2.3


From 21ce873d211a42e315558d6ae09a8bb04508a592 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@deeprootsystems.com>
Date: Thu, 25 Feb 2010 16:49:56 -0800
Subject: davinci: sparse: gpio: void casting

Cleanup usage of void pointers when using genirq.  genirq API
takes and returns void *, where this GPIO API is using those
as __iomem pointers.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 3f7706266ca6..5476ad132044 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -36,6 +36,15 @@ static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
 	return __gpio_to_controller(gpio);
 }
 
+static inline struct gpio_controller __iomem *irq2controller(int irq)
+{
+	struct gpio_controller __iomem *g;
+
+	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+
+	return g;
+}
+
 static int __init davinci_gpio_irq_setup(void);
 
 /*--------------------------------------------------------------------------*/
@@ -161,7 +170,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -170,7 +179,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -186,7 +195,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +224,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -276,7 +285,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -362,7 +371,7 @@ static int __init davinci_gpio_irq_setup(void)
 		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 			set_irq_chip(irq, &gpio_irqchip_unbanked);
 			set_irq_data(irq, (void *) __gpio_mask(gpio));
-			set_irq_chip_data(irq, g);
+			set_irq_chip_data(irq, (__force void *) g);
 			irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
 		}
 
@@ -385,12 +394,12 @@ static int __init davinci_gpio_irq_setup(void)
 
 		/* set up all irqs in this bank */
 		set_irq_chained_handler(bank_irq, gpio_irq_handler);
-		set_irq_chip_data(bank_irq, g);
-		set_irq_data(bank_irq, (void *)irq);
+		set_irq_chip_data(bank_irq, (__force void *) g);
+		set_irq_data(bank_irq, (void *) irq);
 
 		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 			set_irq_chip(irq, &gpio_irqchip);
-			set_irq_chip_data(irq, g);
+			set_irq_chip_data(irq, (__force void *) g);
 			set_irq_data(irq, (void *) __gpio_mask(gpio));
 			set_irq_handler(irq, handle_simple_irq);
 			set_irq_flags(irq, IRQF_VALID);
-- 
cgit v1.2.3


From 8ccfd3f074f75135971905d2413811729e19580e Mon Sep 17 00:00:00 2001
From: Vipin Bhandari <vipin.bhandari@ti.com>
Date: Wed, 10 Mar 2010 14:03:01 +0530
Subject: davinci: da830/omap-l137 evm: add support for GPIO based MMC/SD card
 detection

The DA830/OMAP-L137 EVM has GPIO based card detection logic, but the current
code does not use it.

Add support for GPIO based card detection to avoid reading the card to see
if a card is present or not.

Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index dc19870b23cd..8e670372d7fe 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -229,14 +229,21 @@ static const short da830_evm_mmc_sd_pins[] = {
 };
 
 #define DA830_MMCSD_WP_PIN		GPIO_TO_PIN(2, 1)
+#define DA830_MMCSD_CD_PIN		GPIO_TO_PIN(2, 2)
 
 static int da830_evm_mmc_get_ro(int index)
 {
 	return gpio_get_value(DA830_MMCSD_WP_PIN);
 }
 
+static int da830_evm_mmc_get_cd(int index)
+{
+	return !gpio_get_value(DA830_MMCSD_CD_PIN);
+}
+
 static struct davinci_mmc_config da830_evm_mmc_config = {
 	.get_ro			= da830_evm_mmc_get_ro,
+	.get_cd			= da830_evm_mmc_get_cd,
 	.wires			= 4,
 	.max_freq		= 50000000,
 	.caps			= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
@@ -262,6 +269,14 @@ static inline void da830_evm_init_mmc(void)
 	}
 	gpio_direction_input(DA830_MMCSD_WP_PIN);
 
+	ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
+	if (ret) {
+		pr_warning("da830_evm_init: can not open GPIO %d\n",
+			   DA830_MMCSD_CD_PIN);
+		return;
+	}
+	gpio_direction_input(DA830_MMCSD_CD_PIN);
+
 	ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
 	if (ret) {
 		pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
-- 
cgit v1.2.3


From d154fed7234331dc29240deb04f92f382000e66b Mon Sep 17 00:00:00 2001
From: Vipin Bhandari <vipin.bhandari@ti.com>
Date: Wed, 10 Mar 2010 14:03:02 +0530
Subject: davinci: da830/omap-l137 evm: use 8-wire MMC/SD card support

The merge for 2.6.34 brings in 8-bit support to the DaVinci MMC/SD driver.

This patch updates the platform data for DA830/OMAP-L137 EVM to use 8-wire
support available in the driver.

Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 8e670372d7fe..ea293b8a596a 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -244,7 +244,7 @@ static int da830_evm_mmc_get_cd(int index)
 static struct davinci_mmc_config da830_evm_mmc_config = {
 	.get_ro			= da830_evm_mmc_get_ro,
 	.get_cd			= da830_evm_mmc_get_cd,
-	.wires			= 4,
+	.wires			= 8,
 	.max_freq		= 50000000,
 	.caps			= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 	.version		= MMC_CTLR_VERSION_2,
-- 
cgit v1.2.3


From a7e05065f562ae347db36b0ef644525cd1e89ecd Mon Sep 17 00:00:00 2001
From: Anuj Aggarwal <anuj.aggarwal@ti.com>
Date: Mon, 8 Mar 2010 15:05:58 +0530
Subject: davinci: edma: clear interrupt status for interrupt enabled channels
 only

Currently, the ISR in the EDMA driver clears the pending interrupt for all
channels without regard to whether that channel has a registered callback
or not.

This causes problems for devices like DM355/DM365 where the multimedia
accelerator uses EDMA by polling on the interrupt pending bits of some of the
EDMA channels. Since these channels are actually allocated through the Linux
EDMA driver (by an out-of-kernel module), the same shadow region is used by
Linux and accelerator. There a race between the Linux ISR and the polling code
running on the accelerator on the IPR (interrupt pending register).

This patch fixes the issue by making the ISR clear the interrupts only for
those channels which have interrupt enabled. The channels which are allocated
for the purpose of being polled on by the accelerator will not have a callback
function provided and so will not have IER (interrupt enable register) bits set.

Tested on DM365 and OMAP-L137/L138 with audio and MMC/SD (as EDMA users).

Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
CC: Archith John Bency <archith@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/dma.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 53137387aee1..0bf290befa23 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -359,9 +359,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 
 	while (1) {
 		int j;
-		if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
+		if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
+				edma_shadow0_read_array(ctlr, SH_IER, 0))
 			j = 0;
-		else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
+		else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
+				edma_shadow0_read_array(ctlr, SH_IER, 1))
 			j = 1;
 		else
 			break;
@@ -369,8 +371,9 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				edma_shadow0_read_array(ctlr, SH_IPR, j));
 		for (i = 0; i < 32; i++) {
 			int k = (j << 5) + i;
-			if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
-							(1 << i)) {
+			if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
+					&& (edma_shadow0_read_array(ctlr,
+							SH_IER, j) & BIT(i))) {
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
-- 
cgit v1.2.3


From 8ecf6c54d44c535b2296319aa58567ea9a1db026 Mon Sep 17 00:00:00 2001
From: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Date: Thu, 5 Nov 2009 08:51:34 -0600
Subject: RTC: DaVinci RTC driver

This driver features:

* Alarm support.
* Periodic interrupt by using a timer include into the RTC module.
* The update interrupt is not supported by this RTC module.

This driver was tested on a DM365 EVM by using the rtc-test application
from the Documentation/rtc.txt.

Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: Alessandro Zummo <a.zummo@towertech.it>
---
 drivers/rtc/Kconfig       |  10 +
 drivers/rtc/Makefile      |   1 +
 drivers/rtc/rtc-davinci.c | 673 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 684 insertions(+)
 create mode 100644 drivers/rtc/rtc-davinci.c

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a1303759432..50ac047cd136 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -620,6 +620,16 @@ config RTC_DRV_NUC900
 
 comment "on-CPU RTC drivers"
 
+config RTC_DRV_DAVINCI
+	tristate "TI DaVinci RTC"
+	depends on ARCH_DAVINCI_DM365
+	help
+	  If you say yes here you get support for the RTC on the
+	  DaVinci platforms (DM365).
+
+	  This driver can also be built as a module. If so, the module
+	  will be called rtc-davinci.
+
 config RTC_DRV_OMAP
 	tristate "TI OMAP1"
 	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194a9573..245311a1348f 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K)	+= rtc-bq32k.o
 obj-$(CONFIG_RTC_DRV_BQ4802)	+= rtc-bq4802.o
 obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
 obj-$(CONFIG_RTC_DRV_COH901331)	+= rtc-coh901331.o
+obj-$(CONFIG_RTC_DRV_DAVINCI)	+= rtc-davinci.o
 obj-$(CONFIG_RTC_DRV_DM355EVM)	+= rtc-dm355evm.o
 obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
 obj-$(CONFIG_RTC_DRV_DS1286)	+= rtc-ds1286.o
diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
new file mode 100644
index 000000000000..92a8f6cacda9
--- /dev/null
+++ b/drivers/rtc/rtc-davinci.c
@@ -0,0 +1,673 @@
+/*
+ * DaVinci Power Management and Real Time Clock Driver for TI platforms
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc
+ *
+ * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+/*
+ * The DaVinci RTC is a simple RTC with the following
+ * Sec: 0 - 59 : BCD count
+ * Min: 0 - 59 : BCD count
+ * Hour: 0 - 23 : BCD count
+ * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
+ */
+
+/* PRTC interface registers */
+#define DAVINCI_PRTCIF_PID		0x00
+#define PRTCIF_CTLR			0x04
+#define PRTCIF_LDATA			0x08
+#define PRTCIF_UDATA			0x0C
+#define PRTCIF_INTEN			0x10
+#define PRTCIF_INTFLG			0x14
+
+/* PRTCIF_CTLR bit fields */
+#define PRTCIF_CTLR_BUSY		BIT(31)
+#define PRTCIF_CTLR_SIZE		BIT(25)
+#define PRTCIF_CTLR_DIR			BIT(24)
+#define PRTCIF_CTLR_BENU_MSB		BIT(23)
+#define PRTCIF_CTLR_BENU_3RD_BYTE	BIT(22)
+#define PRTCIF_CTLR_BENU_2ND_BYTE	BIT(21)
+#define PRTCIF_CTLR_BENU_LSB		BIT(20)
+#define PRTCIF_CTLR_BENU_MASK		(0x00F00000)
+#define PRTCIF_CTLR_BENL_MSB		BIT(19)
+#define PRTCIF_CTLR_BENL_3RD_BYTE	BIT(18)
+#define PRTCIF_CTLR_BENL_2ND_BYTE	BIT(17)
+#define PRTCIF_CTLR_BENL_LSB		BIT(16)
+#define PRTCIF_CTLR_BENL_MASK		(0x000F0000)
+
+/* PRTCIF_INTEN bit fields */
+#define PRTCIF_INTEN_RTCSS		BIT(1)
+#define PRTCIF_INTEN_RTCIF		BIT(0)
+#define PRTCIF_INTEN_MASK		(PRTCIF_INTEN_RTCSS \
+					| PRTCIF_INTEN_RTCIF)
+
+/* PRTCIF_INTFLG bit fields */
+#define PRTCIF_INTFLG_RTCSS		BIT(1)
+#define PRTCIF_INTFLG_RTCIF		BIT(0)
+#define PRTCIF_INTFLG_MASK		(PRTCIF_INTFLG_RTCSS \
+					| PRTCIF_INTFLG_RTCIF)
+
+/* PRTC subsystem registers */
+#define PRTCSS_RTC_INTC_EXTENA1		(0x0C)
+#define PRTCSS_RTC_CTRL			(0x10)
+#define PRTCSS_RTC_WDT			(0x11)
+#define PRTCSS_RTC_TMR0			(0x12)
+#define PRTCSS_RTC_TMR1			(0x13)
+#define PRTCSS_RTC_CCTRL		(0x14)
+#define PRTCSS_RTC_SEC			(0x15)
+#define PRTCSS_RTC_MIN			(0x16)
+#define PRTCSS_RTC_HOUR			(0x17)
+#define PRTCSS_RTC_DAY0			(0x18)
+#define PRTCSS_RTC_DAY1			(0x19)
+#define PRTCSS_RTC_AMIN			(0x1A)
+#define PRTCSS_RTC_AHOUR		(0x1B)
+#define PRTCSS_RTC_ADAY0		(0x1C)
+#define PRTCSS_RTC_ADAY1		(0x1D)
+#define PRTCSS_RTC_CLKC_CNT		(0x20)
+
+/* PRTCSS_RTC_INTC_EXTENA1 */
+#define PRTCSS_RTC_INTC_EXTENA1_MASK	(0x07)
+
+/* PRTCSS_RTC_CTRL bit fields */
+#define PRTCSS_RTC_CTRL_WDTBUS		BIT(7)
+#define PRTCSS_RTC_CTRL_WEN		BIT(6)
+#define PRTCSS_RTC_CTRL_WDRT		BIT(5)
+#define PRTCSS_RTC_CTRL_WDTFLG		BIT(4)
+#define PRTCSS_RTC_CTRL_TE		BIT(3)
+#define PRTCSS_RTC_CTRL_TIEN		BIT(2)
+#define PRTCSS_RTC_CTRL_TMRFLG		BIT(1)
+#define PRTCSS_RTC_CTRL_TMMD		BIT(0)
+
+/* PRTCSS_RTC_CCTRL bit fields */
+#define PRTCSS_RTC_CCTRL_CALBUSY	BIT(7)
+#define PRTCSS_RTC_CCTRL_DAEN		BIT(5)
+#define PRTCSS_RTC_CCTRL_HAEN		BIT(4)
+#define PRTCSS_RTC_CCTRL_MAEN		BIT(3)
+#define PRTCSS_RTC_CCTRL_ALMFLG		BIT(2)
+#define PRTCSS_RTC_CCTRL_AIEN		BIT(1)
+#define PRTCSS_RTC_CCTRL_CAEN		BIT(0)
+
+static DEFINE_SPINLOCK(davinci_rtc_lock);
+
+struct davinci_rtc {
+	struct rtc_device 		*rtc;
+	void __iomem			*base;
+	resource_size_t			pbase;
+	size_t				base_size;
+	int				irq;
+};
+
+static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
+			       u32 val, u32 addr)
+{
+	writel(val, davinci_rtc->base + addr);
+}
+
+static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
+{
+	return readl(davinci_rtc->base + addr);
+}
+
+static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
+{
+	while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
+		cpu_relax();
+}
+
+static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
+			       unsigned long val, u8 addr)
+{
+	rtcif_wait(davinci_rtc);
+
+	rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
+	rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
+
+	rtcif_wait(davinci_rtc);
+}
+
+static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
+{
+	rtcif_wait(davinci_rtc);
+
+	rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
+		    PRTCIF_CTLR);
+
+	rtcif_wait(davinci_rtc);
+
+	return rtcif_read(davinci_rtc, PRTCIF_LDATA);
+}
+
+static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
+{
+	while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
+	       PRTCSS_RTC_CCTRL_CALBUSY)
+		cpu_relax();
+}
+
+static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
+{
+	struct davinci_rtc *davinci_rtc = class_dev;
+	unsigned long events = 0;
+	u32 irq_flg;
+	u8 alm_irq, tmr_irq;
+	u8 rtc_ctrl, rtc_cctrl;
+	int ret = IRQ_NONE;
+
+	irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
+		  PRTCIF_INTFLG_RTCSS;
+
+	alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
+		  PRTCSS_RTC_CCTRL_ALMFLG;
+
+	tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
+		  PRTCSS_RTC_CTRL_TMRFLG;
+
+	if (irq_flg) {
+		if (alm_irq) {
+			events |= RTC_IRQF | RTC_AF;
+			rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+			rtc_cctrl |=  PRTCSS_RTC_CCTRL_ALMFLG;
+			rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+		} else if (tmr_irq) {
+			events |= RTC_IRQF | RTC_PF;
+			rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+			rtc_ctrl |=  PRTCSS_RTC_CTRL_TMRFLG;
+			rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+		}
+
+		rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
+				    PRTCIF_INTFLG);
+		rtc_update_irq(davinci_rtc->rtc, 1, events);
+
+		ret = IRQ_HANDLED;
+	}
+
+	return ret;
+}
+
+static int
+davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u8 rtc_ctrl;
+	unsigned long flags;
+	int ret = 0;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+
+	switch (cmd) {
+	case RTC_WIE_ON:
+		rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
+		break;
+	case RTC_WIE_OFF:
+		rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
+		break;
+	case RTC_UIE_OFF:
+	case RTC_UIE_ON:
+		ret = -ENOTTY;
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+	}
+
+	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return ret;
+}
+
+static int convertfromdays(u16 days, struct rtc_time *tm)
+{
+	int tmp_days, year, mon;
+
+	for (year = 2000;; year++) {
+		tmp_days = rtc_year_days(1, 12, year);
+		if (days >= tmp_days)
+			days -= tmp_days;
+		else {
+			for (mon = 0;; mon++) {
+				tmp_days = rtc_month_days(mon, year);
+				if (days >= tmp_days) {
+					days -= tmp_days;
+				} else {
+					tm->tm_year = year - 1900;
+					tm->tm_mon = mon;
+					tm->tm_mday = days + 1;
+					break;
+				}
+			}
+			break;
+		}
+	}
+	return 0;
+}
+
+static int convert2days(u16 *days, struct rtc_time *tm)
+{
+	int i;
+	*days = 0;
+
+	/* epoch == 1900 */
+	if (tm->tm_year < 100 || tm->tm_year > 199)
+		return -EINVAL;
+
+	for (i = 2000; i < 1900 + tm->tm_year; i++)
+		*days += rtc_year_days(1, 12, i);
+
+	*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
+
+	return 0;
+}
+
+static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u16 days = 0;
+	u8 day0, day1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	days |= day1;
+	days <<= 8;
+	days |= day0;
+
+	if (convertfromdays(days, tm) < 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u16 days;
+	u8 rtc_cctrl;
+	unsigned long flags;
+
+	if (convert2days(&days, tm) < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
+
+	rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+	rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
+	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_alarm_irq_enable(struct device *dev,
+					unsigned int enabled)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	if (enabled)
+		rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
+			     PRTCSS_RTC_CCTRL_HAEN |
+			     PRTCSS_RTC_CCTRL_MAEN |
+			     PRTCSS_RTC_CCTRL_ALMFLG |
+			     PRTCSS_RTC_CCTRL_AIEN;
+	else
+		rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u16 days = 0;
+	u8 day0, day1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+	days |= day1;
+	days <<= 8;
+	days |= day0;
+
+	if (convertfromdays(days, &alm->time) < 0)
+		return -EINVAL;
+
+	alm->pending = !!(rtcss_read(davinci_rtc,
+			  PRTCSS_RTC_CCTRL) &
+			PRTCSS_RTC_CCTRL_AIEN);
+	alm->enabled = alm->pending && device_may_wakeup(dev);
+
+	return 0;
+}
+
+static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u16 days;
+
+	if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
+	    && alm->time.tm_year < 0) {
+		struct rtc_time tm;
+		unsigned long now, then;
+
+		davinci_rtc_read_time(dev, &tm);
+		rtc_tm_to_time(&tm, &now);
+
+		alm->time.tm_mday = tm.tm_mday;
+		alm->time.tm_mon = tm.tm_mon;
+		alm->time.tm_year = tm.tm_year;
+		rtc_tm_to_time(&alm->time, &then);
+
+		if (then < now) {
+			rtc_time_to_tm(now + 24 * 60 * 60, &tm);
+			alm->time.tm_mday = tm.tm_mday;
+			alm->time.tm_mon = tm.tm_mon;
+			alm->time.tm_year = tm.tm_year;
+		}
+	}
+
+	if (convert2days(&days, &alm->time) < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u8 rtc_ctrl;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+
+	if (enabled) {
+		while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
+		       & PRTCSS_RTC_CTRL_WDTBUS)
+			cpu_relax();
+
+		rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
+		rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+		rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
+
+		rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
+			    PRTCSS_RTC_CTRL_TMMD |
+			    PRTCSS_RTC_CTRL_TMRFLG;
+	} else
+		rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
+
+	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
+	rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static struct rtc_class_ops davinci_rtc_ops = {
+	.ioctl			= davinci_rtc_ioctl,
+	.read_time		= davinci_rtc_read_time,
+	.set_time		= davinci_rtc_set_time,
+	.alarm_irq_enable	= davinci_rtc_alarm_irq_enable,
+	.read_alarm		= davinci_rtc_read_alarm,
+	.set_alarm		= davinci_rtc_set_alarm,
+	.irq_set_state		= davinci_rtc_irq_set_state,
+	.irq_set_freq		= davinci_rtc_irq_set_freq,
+};
+
+static int __init davinci_rtc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct davinci_rtc *davinci_rtc;
+	struct resource *res, *mem;
+	int ret = 0;
+
+	davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
+	if (!davinci_rtc) {
+		dev_dbg(dev, "could not allocate memory for private data\n");
+		return -ENOMEM;
+	}
+
+	davinci_rtc->irq = platform_get_irq(pdev, 0);
+	if (davinci_rtc->irq < 0) {
+		dev_err(dev, "no RTC irq\n");
+		ret = davinci_rtc->irq;
+		goto fail1;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "no mem resource\n");
+		ret = -EINVAL;
+		goto fail1;
+	}
+
+	davinci_rtc->pbase = res->start;
+	davinci_rtc->base_size = resource_size(res);
+
+	mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
+				 pdev->name);
+	if (!mem) {
+		dev_err(dev, "RTC registers at %08x are not free\n",
+			davinci_rtc->pbase);
+		ret = -EBUSY;
+		goto fail1;
+	}
+
+	davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
+	if (!davinci_rtc->base) {
+		dev_err(dev, "unable to ioremap MEM resource\n");
+		ret = -ENOMEM;
+		goto fail2;
+	}
+
+	davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
+				    &davinci_rtc_ops, THIS_MODULE);
+	if (IS_ERR(davinci_rtc->rtc)) {
+		dev_err(dev, "unable to register RTC device, err %ld\n",
+				PTR_ERR(davinci_rtc->rtc));
+		goto fail3;
+	}
+
+	rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
+	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
+	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
+
+	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
+	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
+
+	ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
+			  IRQF_DISABLED, "davinci_rtc", davinci_rtc);
+	if (ret < 0) {
+		dev_err(dev, "unable to register davinci RTC interrupt\n");
+		goto fail4;
+	}
+
+	/* Enable interrupts */
+	rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
+	rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
+			    PRTCSS_RTC_INTC_EXTENA1);
+
+	rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
+
+	platform_set_drvdata(pdev, davinci_rtc);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	return 0;
+
+fail4:
+	rtc_device_unregister(davinci_rtc->rtc);
+fail3:
+	iounmap(davinci_rtc->base);
+fail2:
+	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
+fail1:
+	kfree(davinci_rtc);
+
+	return ret;
+}
+
+static int __devexit davinci_rtc_remove(struct platform_device *pdev)
+{
+	struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
+
+	free_irq(davinci_rtc->irq, davinci_rtc);
+
+	rtc_device_unregister(davinci_rtc->rtc);
+
+	iounmap(davinci_rtc->base);
+	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
+
+	platform_set_drvdata(pdev, NULL);
+
+	kfree(davinci_rtc);
+
+	return 0;
+}
+
+static struct platform_driver davinci_rtc_driver = {
+	.probe		= davinci_rtc_probe,
+	.remove		= __devexit_p(davinci_rtc_remove),
+	.driver		= {
+		.name = "rtc_davinci",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init rtc_init(void)
+{
+	return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
+}
+module_init(rtc_init);
+
+static void __exit rtc_exit(void)
+{
+	platform_driver_unregister(&davinci_rtc_driver);
+}
+module_exit(rtc_exit);
+
+MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
+MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
+MODULE_LICENSE("GPL");
-- 
cgit v1.2.3


From 9c0a342c45b2d98209ac473ea7a429ddd5c1b473 Mon Sep 17 00:00:00 2001
From: Sekhar Nori <nsekhar@ti.com>
Date: Sun, 7 Mar 2010 18:05:54 +0530
Subject: rtc: omap: let device wakeup capability be configured from chip init
 logic

The rtc-omap driver currently hardcodes the RTC wakeup capability
to be "not capable". While this seems to be true for existing OMAP1
boards which are not wired for this, the DA850/OMAP-L138 SoC, the
RTC can always be wake up source from its "deep sleep" mode.

This patch lets the wakeup capability to be set from platform data and
does not override the setting from the driver. For DA850/OMAP-L138, this
is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()

Note that this patch does not change the behavior on any existing OMAP1
board since the platform device registration sets the wakeup capability
to 0 by default.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 drivers/rtc/rtc-omap.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 64d9727b7229..73377b0d65da 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -34,7 +34,8 @@
  * Board-specific wiring options include using split power mode with
  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
- * low power modes).  See the BOARD-SPECIFIC CUSTOMIZATION comment.
+ * low power modes) for OMAP1 boards (OMAP-L138 has this built into
+ * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  */
 
 #define OMAP_RTC_BASE			0xfffb4800
@@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
 
 	/* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
 	 *
-	 *  - Boards wired so that RTC_WAKE_INT does something, and muxed
-	 *    right (W13_1610_RTC_WAKE_INT is the default after chip reset),
-	 *    should initialize the device wakeup flag appropriately.
+	 *  - Device wake-up capability setting should come through chip
+	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
+	 *    flag in the platform device if the board is wired right for
+	 *    being woken up by RTC alarm. For OMAP-L138, this capability
+	 *    is built into the SoC by the "Deep Sleep" capability.
 	 *
 	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
 	 *    rather than nPWRON_RESET, should forcibly enable split
 	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
 	 *    is write-only, and always reads as zero...)
 	 */
-	device_init_wakeup(&pdev->dev, 0);
 
 	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
 		pr_info("%s: split power mode\n", pdev->name);
-- 
cgit v1.2.3


From b722049d7e60356fe04bcac6065a7c8b1c64c06f Mon Sep 17 00:00:00 2001
From: Cyril Chemparathy <cyril@ti.com>
Date: Thu, 25 Mar 2010 17:43:44 -0400
Subject: Davinci: allow SOCs based on other ARM CPUs

Preliminary modification prior to adding support for TNETV107X based on
ARM1176.  This change allows for CPUs other than ARM926T to be used for Davinci
derivative SoCs.  Existing devices (DA8x and DMx) operate unchanged.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/Kconfig              | 1 -
 arch/arm/mach-davinci/Kconfig | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92622eb5cc0d..1151d1afd756 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -776,7 +776,6 @@ config ARCH_NOMADIK
 
 config ARCH_DAVINCI
 	bool "TI DaVinci"
-	select CPU_ARM926T
 	select GENERIC_TIME
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_GPIO
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0ebe185610bf..0316e201ada0 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -7,6 +7,7 @@ config CP_INTC
 	bool
 
 config ARCH_DAVINCI_DMx
+	select CPU_ARM926T
 	bool
 
 menu "TI DaVinci Implementations"
@@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
 	select ARCH_HAS_CPUFREQ
 
 config ARCH_DAVINCI_DA8XX
+	select CPU_ARM926T
 	bool
 
 config ARCH_DAVINCI_DM365
-- 
cgit v1.2.3


From 8ca2e597fc8f3337cef1f8febab482fe8c52b004 Mon Sep 17 00:00:00 2001
From: Cyril Chemparathy <cyril@ti.com>
Date: Thu, 25 Mar 2010 17:43:45 -0400
Subject: Davinci: enable timer clock before use

timer_init() programs timer64 hardware.  The module should ideally be brought
out of reset before this happens.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/time.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 9e0b106b4f5f..b21f7633d9a8 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -361,13 +361,13 @@ static void __init davinci_timer_init(void)
 		}
 	}
 
-	/* init timer hw */
-	timer_init();
-
 	timer_clk = clk_get(NULL, "timer0");
 	BUG_ON(IS_ERR(timer_clk));
 	clk_enable(timer_clk);
 
+	/* init timer hw */
+	timer_init();
+
 	davinci_clock_tick_rate = clk_get_rate(timer_clk);
 
 	/* setup clocksource */
-- 
cgit v1.2.3


From 449ef7f6a9c732657938b222f8804d3e34a3603e Mon Sep 17 00:00:00 2001
From: Cyril Chemparathy <cyril@ti.com>
Date: Thu, 25 Mar 2010 17:43:46 -0400
Subject: Davinci: cpintc host map configuration

Host map configuration instructs the interrupt controller to route interrupt
channels to FIQ or IRQ lines.  Currently, DA8xx family of devices leave these
registers at their reset-default values.

TNETV107X however does not have sane reset defaults, and therefore this
architecture needs to reconfigure the host-map such that channels 0 and 1
go to FIQ, and the remaining channels raise IRQs.

This patch adds an optional host map argument to cp_intc_init() for this.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c      | 2 +-
 arch/arm/mach-davinci/board-da850-evm.c      | 2 +-
 arch/arm/mach-davinci/cp_intc.c              | 6 +++++-
 arch/arm/mach-davinci/include/mach/cp_intc.h | 2 +-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index ea293b8a596a..db5ac0f3788e 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -569,7 +569,7 @@ static __init void da830_evm_irq_init(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
 	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios);
+			soc_info->intc_irq_prios, NULL);
 }
 
 static void __init da830_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 411284d0b0fa..ef691ae5e67a 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -741,7 +741,7 @@ static __init void da850_evm_irq_init(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
 	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios);
+			soc_info->intc_irq_prios, NULL);
 }
 
 static void __init da850_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 37311d1830eb..2a8d26ee4bbf 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -101,7 +101,7 @@ static struct irq_chip cp_intc_irq_chip = {
 };
 
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio)
+			 u8 *irq_prio, u32 *host_map)
 {
 	unsigned num_reg	= BITS_TO_LONGS(num_irq);
 	int i;
@@ -157,6 +157,10 @@ void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
 			cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
 	}
 
+	if (host_map)
+		for (i = 0; host_map[i] != -1; i++)
+			cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
+
 	/* Set up genirq dispatching for cp_intc */
 	for (i = 0; i < num_irq; i++) {
 		set_irq_chip(i, &cp_intc_irq_chip);
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index c4d27eec8064..121b114df755 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,6 +52,6 @@
 #define CP_INTC_VECTOR_ADDR(n)		(0x2000 + (n << 2))
 
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio);
+			 u8 *irq_prio, u32 *host_map);
 
 #endif	/* __ASM_HARDWARE_CP_INTC_H */
-- 
cgit v1.2.3


From 52958be3ad6e2b72a5943718f339ed4e11685739 Mon Sep 17 00:00:00 2001
From: Cyril Chemparathy <cyril@ti.com>
Date: Thu, 25 Mar 2010 17:43:47 -0400
Subject: Davinci: support LPSC SwRstDisable state

The current clock control code always gates the clock (PSC state Disable = 2)
on clk_disable().  Some on-chip peripherals (e.g. LCD controller on TNETV107X)
need to be put into SwRstDisable = 0 on clock disable, to maintain
hardware sanity.

This patch extends the davinci_psc_config() arguments to pass in the desired
module state instead of a boolean enable/disable.  Further, clk_disable() now
checks for the PSC_SWRSTDISABLE clk flag before selecting the target state.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/clock.c            | 12 +++++++++---
 arch/arm/mach-davinci/clock.h            |  7 ++++---
 arch/arm/mach-davinci/include/mach/psc.h |  8 +++++++-
 arch/arm/mach-davinci/psc.c              |  3 +--
 4 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 058c77f72a07..5de60ae57903 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -43,7 +43,8 @@ static void __clk_enable(struct clk *clk)
 	if (clk->parent)
 		__clk_enable(clk->parent);
 	if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
+		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+				PSC_STATE_ENABLE);
 }
 
 static void __clk_disable(struct clk *clk)
@@ -52,7 +53,9 @@ static void __clk_disable(struct clk *clk)
 		return;
 	if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
 	    (clk->flags & CLK_PSC))
-		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
+		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+				(clk->flags & PSC_SWRSTDISABLE) ?
+				PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
 	if (clk->parent)
 		__clk_disable(clk->parent);
 }
@@ -234,7 +237,10 @@ static int __init clk_disable_unused(void)
 			continue;
 
 		pr_info("Clocks: disable unused %s\n", ck->name);
-		davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
+
+		davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+				(ck->flags & PSC_SWRSTDISABLE) ?
+				PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
 	}
 	spin_unlock_irq(&clockfw_lock);
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index aa0a61150325..53a0f7b90119 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -101,10 +101,11 @@ struct clk {
 
 /* Clock flags: SoC-specific flags start at BIT(16) */
 #define ALWAYS_ENABLED		BIT(1)
-#define CLK_PSC                 BIT(2)
-#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
+#define CLK_PSC			BIT(2)
+#define PSC_DSP			BIT(3) /* PSC uses DSP domain, not ARM */
 #define CLK_PLL			BIT(4) /* PLL-derived clock */
-#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
+#define PRE_PLL			BIT(5) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLE	BIT(6) /* Disable state is SwRstDisable */
 
 #define CLK(dev, con, ck) 	\
 	{			\
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 651f6d8158fa..7dd2962ad586 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -189,13 +189,19 @@
 #define MDSTAT		0x800
 #define MDCTL		0xA00
 
+/* PSC module states */
+#define PSC_STATE_SWRSTDISABLE	0
+#define PSC_STATE_SYNCRST	1
+#define PSC_STATE_DISABLE	2
+#define PSC_STATE_ENABLE	3
+
 #define MDSTAT_STATE_MASK 0x1f
 
 #ifndef __ASSEMBLER__
 
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-		unsigned int id, char enable);
+		unsigned int id, u32 next_state);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index adf6b5c7f1e5..d7cb438c4df6 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -47,12 +47,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-		unsigned int id, char enable)
+		unsigned int id, u32 next_state)
 {
 	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
 	void __iomem *psc_base;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
 
 	if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
 		pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
-- 
cgit v1.2.3


From 3821d10a538ac9d750987badd404c8f860ffa774 Mon Sep 17 00:00:00 2001
From: Cyril Chemparathy <cyril@ti.com>
Date: Thu, 25 Mar 2010 17:43:48 -0400
Subject: Davinci: promote da8xx_pinmux_setup()

Rename da8xx_pinmux_setup() to davinci_cfg_reg_list() and promote it for use in
other SOCs that may need the ability to configure multiple pins in one shot.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c    | 14 +++++++-------
 arch/arm/mach-davinci/board-da850-evm.c    | 18 +++++++++---------
 arch/arm/mach-davinci/include/mach/da8xx.h |  6 ------
 arch/arm/mach-davinci/include/mach/mux.h   |  5 +++++
 arch/arm/mach-davinci/mux.c                |  3 +--
 5 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index db5ac0f3788e..925705649ed0 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -157,7 +157,7 @@ static __init void da830_evm_usb_init(void)
 				   __func__, ret);
 	}
 
-	ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
+	ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
 	if (ret) {
 		pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
 			   __func__, ret);
@@ -254,7 +254,7 @@ static inline void da830_evm_init_mmc(void)
 {
 	int ret;
 
-	ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
+	ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
 	if (ret) {
 		pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
 				ret);
@@ -407,7 +407,7 @@ static inline void da830_evm_init_nand(int mux_mode)
 		return;
 	}
 
-	ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
+	ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
 	if (ret)
 		pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
 				ret);
@@ -427,7 +427,7 @@ static inline void da830_evm_init_lcdc(int mux_mode)
 {
 	int ret;
 
-	ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
+	ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
 	if (ret)
 		pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
 				ret);
@@ -507,7 +507,7 @@ static __init void da830_evm_init(void)
 		pr_warning("da830_evm_init: edma registration failed: %d\n",
 				ret);
 
-	ret = da8xx_pinmux_setup(da830_i2c0_pins);
+	ret = davinci_cfg_reg_list(da830_i2c0_pins);
 	if (ret)
 		pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
 				ret);
@@ -523,7 +523,7 @@ static __init void da830_evm_init(void)
 	soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
 	soc_info->emac_pdata->rmii_en = 1;
 
-	ret = da8xx_pinmux_setup(da830_cpgmac_pins);
+	ret = davinci_cfg_reg_list(da830_cpgmac_pins);
 	if (ret)
 		pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
 				ret);
@@ -542,7 +542,7 @@ static __init void da830_evm_init(void)
 	i2c_register_board_info(1, da830_evm_i2c_devices,
 			ARRAY_SIZE(da830_evm_i2c_devices));
 
-	ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
+	ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
 	if (ret)
 		pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
 				ret);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index ef691ae5e67a..6c137e0492ff 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void)
 	int ret = 0;
 
 	if (ui_card_detected & !HAS_MMC) {
-		ret = da8xx_pinmux_setup(da850_nand_pins);
+		ret = davinci_cfg_reg_list(da850_nand_pins);
 		if (ret)
 			pr_warning("da850_evm_init: nand mux setup failed: "
 					"%d\n", ret);
 
-		ret = da8xx_pinmux_setup(da850_nor_pins);
+		ret = davinci_cfg_reg_list(da850_nor_pins);
 		if (ret)
 			pr_warning("da850_evm_init: nor mux setup failed: %d\n",
 				ret);
@@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void)
 
 	if (rmii_en) {
 		val |= BIT(8);
-		ret = da8xx_pinmux_setup(da850_rmii_pins);
+		ret = davinci_cfg_reg_list(da850_rmii_pins);
 		pr_info("EMAC: RMII PHY configured, MII PHY will not be"
 							" functional\n");
 	} else {
 		val &= ~BIT(8);
-		ret = da8xx_pinmux_setup(da850_cpgmac_pins);
+		ret = davinci_cfg_reg_list(da850_cpgmac_pins);
 		pr_info("EMAC: MII PHY configured, RMII PHY will not be"
 							" functional\n");
 	}
@@ -626,7 +626,7 @@ static __init void da850_evm_init(void)
 		pr_warning("da850_evm_init: edma registration failed: %d\n",
 				ret);
 
-	ret = da8xx_pinmux_setup(da850_i2c0_pins);
+	ret = davinci_cfg_reg_list(da850_i2c0_pins);
 	if (ret)
 		pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
 				ret);
@@ -643,7 +643,7 @@ static __init void da850_evm_init(void)
 				ret);
 
 	if (HAS_MMC) {
-		ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
+		ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
 		if (ret)
 			pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
 					" %d\n", ret);
@@ -679,20 +679,20 @@ static __init void da850_evm_init(void)
 	__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
 	__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
 
-	ret = da8xx_pinmux_setup(da850_mcasp_pins);
+	ret = davinci_cfg_reg_list(da850_mcasp_pins);
 	if (ret)
 		pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
 				ret);
 
 	da8xx_register_mcasp(0, &da850_evm_snd_data);
 
-	ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
+	ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
 	if (ret)
 		pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
 				ret);
 
 	/* Handle board specific muxing for LCD here */
-	ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
+	ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
 	if (ret)
 		pr_warning("da850_evm_init: evm specific lcd mux setup "
 				"failed: %d\n",	ret);
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 03acfd39042b..33471c9cbca3 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -146,10 +146,4 @@ extern const short da850_mmcsd0_pins[];
 extern const short da850_nand_pins[];
 extern const short da850_nor_pins[];
 
-#ifdef CONFIG_DAVINCI_MUX
-int da8xx_pinmux_setup(const short pins[]);
-#else
-static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
-#endif
-
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 2a68c1d8a24b..48888db00fad 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -907,9 +907,14 @@ enum davinci_da850_index {
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
+extern int davinci_cfg_reg_list(const short pins[]);
 #else
 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
+static inline int davinci_cfg_reg_list(const short pins[])
+{
+	return 0;
+}
 #endif
 
 #endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index c942c893a2eb..e9d530a8f79f 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,7 +21,6 @@
 
 #include <mach/mux.h>
 #include <mach/common.h>
-#include <mach/da8xx.h>
 
 /*
  * Sets the DAVINCI MUX register based on the table
@@ -92,7 +91,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 }
 EXPORT_SYMBOL(davinci_cfg_reg);
 
-int da8xx_pinmux_setup(const short pins[])
+int __init_or_module davinci_cfg_reg_list(const short pins[])
 {
 	int i, error = -EINVAL;
 
-- 
cgit v1.2.3


From 0e23f71d60bdb4c202402c5f5c709deacc5d0f17 Mon Sep 17 00:00:00 2001
From: Cyril Chemparathy <cyril@ti.com>
Date: Thu, 25 Mar 2010 17:43:49 -0400
Subject: Davinci: tnetv107x pin list

Added list of muxed pins on the tnetv107x SOC.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/mux.h | 269 +++++++++++++++++++++++++++++++
 1 file changed, 269 insertions(+)

diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 48888db00fad..863890342a0a 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -904,6 +904,275 @@ enum davinci_da850_index {
 	DA850_RTC_ALARM,
 };
 
+enum davinci_tnetv107x_index {
+	TNETV107X_ASR_A00,
+	TNETV107X_GPIO32,
+	TNETV107X_ASR_A01,
+	TNETV107X_GPIO33,
+	TNETV107X_ASR_A02,
+	TNETV107X_GPIO34,
+	TNETV107X_ASR_A03,
+	TNETV107X_GPIO35,
+	TNETV107X_ASR_A04,
+	TNETV107X_GPIO36,
+	TNETV107X_ASR_A05,
+	TNETV107X_GP