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2026-01-21Input: gpio_decoder - replace custom loop by gpiod_get_array_value_cansleep()Andy Shevchenko1-15/+15
There is a custom loop that repeats parts of gpiod_get_array_value_cansleep(). Use that in conjunction with bitmap API to make code shorter and easier to follow. With this done, add an upper check for amount of GPIOs given based on the driver's code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-4-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - unify messages with help of dev_err_probe()Andy Shevchenko1-16/+10
Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-3-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - make use of device propertiesAndy Shevchenko1-5/+4
Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-2-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21drm/amdgpu: fix type for wptr in ring backupAlex Deucher1-1/+1
Needs to be a u64. Fixes: 77cc0da39c7c ("drm/amdgpu: track ring state associated with a fence") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 56fff1941abd3ca3b6f394979614ca7972552f7f)
2026-01-21drm/amdgpu: Fix validating flush_gpu_tlb_pasid()Timur Kristóf1-2/+4
When a function holds a lock and we return without unlocking it, it deadlocks the kernel. We should always unlock before returning. This commit fixes suspend/resume on SI. Tested on two Tahiti GPUs: FirePro W9000 and R9 280X. Fixes: f4db9913e4d3 ("drm/amdgpu: validate the flush_gpu_tlb_pasid()") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202601190121.z9C0uml5-lkp@intel.com/ Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit e3a6eff92bbd960b471966d9afccb4d584546d17)
2026-01-21drm/amd/pm: Workaround SI powertune issue on Radeon 430 (v2)Timur Kristóf1-1/+12
Radeon 430 and 520 are OEM GPUs from 2016~2017 They have the same device id: 0x6611 and revision: 0x87 On the Radeon 430, powertune is buggy and throttles the GPU, never allowing it to reach its maximum SCLK. Work around this bug by raising the TDP limits we program to the SMC from 24W (specified by the VBIOS on Radeon 430) to 32W. Disabling powertune entirely is not a viable workaround, because it causes the Radeon 520 to heat up above 100 C, which I prefer to avoid. Additionally, revise the maximum SCLK limit. Considering the above issue, these GPUs never reached a high SCLK on Linux, and the workarounds were added before the GPUs were released, so the workaround likely didn't target these specifically. Use 780 MHz (the maximum SCLK according to the VBIOS on the Radeon 430). Note that the Radeon 520 VBIOS has a higher maximum SCLK: 905 MHz, but in practice it doesn't seem to perform better with the higher clock, only heats up more. v2: Move the workaround to si_populate_smc_tdp_limits. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 966d70f1e160bdfdecaf7ff2b3f22ad088516e9f)
2026-01-21drm/amd/pm: Don't clear SI SMC table when setting power limitTimur Kristóf1-10/+0
There is no reason to clear the SMC table. We also don't need to recalculate the power limit then. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit e214d626253f5b180db10dedab161b7caa41f5e9)
2026-01-21drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT settingTimur Kristóf1-4/+4
Use WREG32 to write mmCG_THERMAL_INT. This is a direct access register. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 2555f4e4a741d31e0496572a8ab4f55941b4e30e)
2026-01-21drm/amdgpu: rename amdgpu_fence_driver_guilty_force_completion()Alex Deucher3-6/+6
The function no longer signals the fence so rename it to better match what it does. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu: fix type for wptr in ring backupAlex Deucher1-1/+1
Needs to be a u64. Fixes: 77cc0da39c7c ("drm/amdgpu: track ring state associated with a fence") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu: mark invalid records with U64_MAXGangliang Xie1-0/+6
set retired_page of invalid ras records to U64_MAX, and skip them when reading ras records Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu: Avoid excessive dmesg logLijo Lazar1-1/+2
KIQ access is not guaranteed to work reliably under all reset situations. Avoid flooding dmesg with HDP flush failure messages. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu: Fix validating flush_gpu_tlb_pasid()Timur Kristóf1-2/+4
When a function holds a lock and we return without unlocking it, it deadlocks the kernel. We should always unlock before returning. This commit fixes suspend/resume on SI. Tested on two Tahiti GPUs: FirePro W9000 and R9 280X. Fixes: f4db9913e4d3 ("drm/amdgpu: validate the flush_gpu_tlb_pasid()") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202601190121.z9C0uml5-lkp@intel.com/ Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: simplify svm_range_unmap_from_gpus()Yury Norov1-4/+1
The function calls bitmap_or() followed by for_each_set_bit(). Switch it to the dedicated for_each_or_bit() and drop the temporary bitmap. Signed-off-by: Yury Norov <ynorov@nvidia.com> Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: Do not include VGPR MSBs in saved PC during saveLancelot Six2-4/+4
The current trap handler uses the top bits of ttmp1 to store a copy of sq_wave_mode.*vgpr_msb (except for src2_vgpr_msb). This is so the effective values in sq_wave_mode can be cleared to ensure correct behavior of the trap handler. When saving sq_wave_mode, the trap handler correctly rebuilds the expected value (with *vgpr_msb restored), so the save area is correct. However, the PC itself is copied from ttmp[0:1], which contains the wave's PC as well as the saved MSBs. The debugger reads the PC from the save area and is confused when non-0 values from VGPR_MSBs are present. This patch fixes this by saving the PC in the save area's PC slot, not the composite of the PC and VGPR_MSBs. On restore, the VGPR_MSBs are restored from sq_wave_mode. Signed-off-by: Lancelot Six <lancelot.six@amd.com> Tested-by: Alexey Kondratiev <Alexey.Kondratiev@amd.com> Reviewed-by: Jay Cornwall <jay.cornwall@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Correct comment above power2_cap attributesTimur Kristóf1-1/+1
Previously only Van Gogh supported this, but that is not true anymore since: commit 12c958d1db36 ("drm/amd/pm: Expose ppt1 limit for gc_v9_5_0") Update the comment to reflect that. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Return -EOPNOTSUPP when can't read power limitTimur Kristóf1-1/+1
So that hwmon_attributes_visible() will see that the power2_cap attributes should not be visible on GPUs that don't support the get_power_limit() function. This fixes an error when running the "sensors" command on SI. Fixes: 12c958d1db36 ("drm/amd/pm: Expose ppt1 limit for gc_v9_5_0") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Workaround SI powertune issue on Radeon 430 (v2)Timur Kristóf1-1/+12
Radeon 430 and 520 are OEM GPUs from 2016~2017 They have the same device id: 0x6611 and revision: 0x87 On the Radeon 430, powertune is buggy and throttles the GPU, never allowing it to reach its maximum SCLK. Work around this bug by raising the TDP limits we program to the SMC from 24W (specified by the VBIOS on Radeon 430) to 32W. Disabling powertune entirely is not a viable workaround, because it causes the Radeon 520 to heat up above 100 C, which I prefer to avoid. Additionally, revise the maximum SCLK limit. Considering the above issue, these GPUs never reached a high SCLK on Linux, and the workarounds were added before the GPUs were released, so the workaround likely didn't target these specifically. Use 780 MHz (the maximum SCLK according to the VBIOS on the Radeon 430). Note that the Radeon 520 VBIOS has a higher maximum SCLK: 905 MHz, but in practice it doesn't seem to perform better with the higher clock, only heats up more. v2: Move the workaround to si_populate_smc_tdp_limits. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Don't clear SI SMC table when setting power limitTimur Kristóf1-10/+0
There is no reason to clear the SMC table. We also don't need to recalculate the power limit then. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: gfx12.1 trap handler support for expert scheduling modeJay Cornwall2-189/+218
- Leave DEP_MODE unchanged as it is ignored in the trap handler - Save/restore SCHED_MODE (gfx12.0 saves in ttmp11) Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: gfx12.1 cluster barrier context save workaroundJay Cornwall2-20/+47
Trap cluster barrier may not serialize with user cluster barrier under some circumstances. Add a check for pending user cluster barrier complete. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Tested-by: Gang Ba <Gang.Ba@amd.com> Cc: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: Fix scalar load ordering in gfx12.1 trap handlerJay Cornwall2-5/+5
Scalar loads may arrive out-of-order with respect to KMCNT. The affected code expects the two loads to arrive in-order. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Joseph Greathouse <joseph.greathouse@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: Sync trap handler binary with sourceJay Cornwall2-896/+825
Binary and source desynced during branch activity. Source merge also introduced compile error. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu/vcn5.0.1: rework reset handlingJesse.Zhang2-3/+101
Resetting VCN resets the entire tile, including jpeg. When resetting the VCN, we need to ensure that JPEG data blocks are accessible and we also need to handle the JPEG queue. Add a helper function to restore the JPEG queue during the VCN reset. v2: split the jpeg helper in two, in the top helper we can stop the sched workqueues and attempt to wait for any outstanding fences. Then in the bottom helper, we can force completion, re-init the rings, and restart the sched workqueues (Alex) v3: merge patches 4 and 5 into one patch (Alex) Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu/vcn4.0.3: rework reset handlingJesse.Zhang2-3/+100
Resetting VCN resets the entire tile, including jpeg. When resetting the VCN, we need to ensure that JPEG data blocks are accessible and we also need to handle the JPEG queue. Add a helper function to restore the JPEG queue during the VCN reset. v2: split the jpeg helper in two, in the top helper we can stop the sched workqueues and attempt to wait for any outstanding fences. Then in the bottom helper, we can force completion, re-init the rings, and restart the sched workqueues (Alex) v3: merge patches 1 and 2 into one patch (Alex) Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu/vcn4.0.3: implement DPG pause mode handling for VCN 4.0.3Jesse.Zhang1-0/+41
For MI projects, when Dynamic Power Gating (DPG) is enabled, VCN reset operations should be performed with DPG in pause mode. Otherwise, the hardware may perform undesirable reset operations Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT settingTimur Kristóf1-4/+4
Use WREG32 to write mmCG_THERMAL_INT. This is a direct access register. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21thermal: renesas: rzg3e: add support for RZ/T2H and RZ/N2HCosmin Tanislav1-0/+27
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration via SMC SIP and do not have a reset for the TSU peripheral, and use different minimum and maximum temperature values compared to the already supported RZ/G3E. Although the calibration data is stored in an OTP memory, the OTP itself is not memory-mapped, access to it is done through an OTP controller. The OTP controller is only accessible from the secure world, but the temperature calibration data stored in the OTP is exposed via SMC. Add support for retrieving the calibration data using arm_smcc_smc(). Add a compatible for RZ/T2H, RZ/N2H can use it as a fallback. Reviewed-by: John Madieu <john.madieu.xa@bp.renesas.com> Tested-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260108195223.193531-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-21thermal: renesas: rzg3e: make calibration value retrieval per-chipCosmin Tanislav1-42/+29
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration data via SMC SIP calls. To prepare for supporting these SoCs, do the following changes. Rename rzg3e_thermal_parse_dt() to rzg3e_thermal_get_syscon_trim(). Move the syscon usage out of rzg3e_thermal_get_calibration() and into rzg3e_thermal_get_syscon_trim() and remove single-use variables from the private state. Place a pointer to rzg3e_thermal_get_syscon_trim() into the chip-specific struct, and use it in the probe function to retrieve the calibration values. Now that syscon usage has been moved out of rzg3e_thermal_get_calibration(), remove it and inline the calibration validation into the probe function. Also, reuse the TSU_CODE_MAX macro to mask the calibration values, as GEMASK(11, 0) and 0xFFF are equivalent, and replace the hardcoded 0xFFF with TSU_CODE_MAX in the calibration validation. Reviewed-by: John Madieu <john.madieu.xa@bp.renesas.com> Tested-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260108195223.193531-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-21thermal: renesas: rzg3e: make min and max temperature per-chipCosmin Tanislav1-12/+23
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have different minimum and maximum temperatures compared to the already supported RZ/G3E. Prepare for them by moving these into a chip-specific struct. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: John Madieu <john.madieu.xa@bp.renesas.com> Tested-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Link: https://patch.msgid.link/20260108195223.193531-3-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-21thermal: renesas: rzg3e: make reset optionalCosmin Tanislav1-1/+1
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have a reset line. Prepare for them by making it optional. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: John Madieu <john.madieu.xa@bp.renesas.com> Tested-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Link: https://patch.msgid.link/20260108195223.193531-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-21pwm: tiehrpwm: Enable pwmchip's parent device before setting configurationGokul Praveen1-4/+2
The period and duty cycle configurations on J7200 and J784S4 SoCs does not get reflected after setting them using sysfs nodes. This is because at the end of ehrpwm_pwm_config function, the put_sync function is called which resets the hardware. Hold the PWM controller out of low-power mode during .apply() to make sure it accepts the writes to its registers. This renders the calls to pm_runtime_get_sync() and pm_runtime_put_sync() in ehrpwm_pwm_config() into no-ops, so these can be dropped. Fixes: 5f027d9b83db ("pwm: tiehrpwm: Implement .apply() callback") Signed-off-by: Gokul Praveen <g-praveen@ti.com> Suggested-by: Uwe Kleine-König <ukleinek@kernel.org> Link: https://patch.msgid.link/20260121061134.15466-1-g-praveen@ti.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2026-01-21Merge tag 'soc-fixes-6.19-2' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "The main changes are devicetree updates for qualcomm and rockchips arm64 platforms, fixing minor mistakes in SoC and board specific settings: - GPIO settings for Pinephone Pro buttons - Register ranges for rk3576 GPU - Power domains on sc8280xp - Clocks on qcom talos - dtc warnings for extraneous properties, nonstandard node names and undocument identifiers The Tegra210 platform gets a single revert for a devicetree change that caused a 6.19 regression. On 32-bit Arm, we have trivial fixes for Microchip SAMA7 devicetree files and NPCM Kconfig, as well as Andrew Jeffery being officially listed as MAINTAINER for NPCM. A single driver fix is for Qualcomm RPMHD power domains, bringing the driver up to date with a devicetree change that added additional power domains to be enabled" * tag 'soc-fixes-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (27 commits) MAINTAINERS: Add Andrew as M: to ARM/NUVOTON NPCM ARCHITECTURE MAINTAINERS: update email address for Yixun Lan Revert "arm64: tegra: Add interconnect properties for Tegra210" arm64: dts: rockchip: Drop unsupported properties arm64: dts: rockchip: Fix gpio pinctrl node names arm64: dts: rockchip: Fix pinctrl property typo on rk3326-odroid-go3 arm64: dts: rockchip: Drop "sitronix,st7789v" fallback compatible from rk3568-wolfvision ARM: dts: microchip: sama7d65: fix size-cells property for i2c3 ARM: dts: microchip: sama7d65: fix the ranges property for flx9 arm: npcm: drop unused Kconfig ERRATA symbol arm64: dts: rockchip: Fix wrong register range of rk3576 gpu arm64: dts: rockchip: Configure MCLK for analog sound on NanoPi M5 arm64: dts: rockchip: Fix headphones widget name on NanoPi M5 ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290 arm64: dts: rockchip: remove redundant max-link-speed from nanopi-r4s arm64: dts: rockchip: remove dangerous max-link-speed from helios64 arm64: dts: rockchip: fix unit-address for RK3588 NPU's core1 and core2's IOMMU arm64: dts: rockchip: Fix wifi interrupts flag on Sakura Pi RK3308B arm64: dts: qcom: sm8650: Fix compile warnings in USB controller node arm64: dts: qcom: sm8550: Fix compile warnings in USB controller node ...
2026-01-21drm/bridge: fix kdoc syntaxLuca Ceresoli1-0/+3
Use the correct kdoc syntax for bullet list. Fixes kdoc error and warning: Documentation/gpu/drm-kms-helpers:197: ./drivers/gpu/drm/drm_bridge.c:1519: ERROR: Unexpected indentation. [docutils] Documentation/gpu/drm-kms-helpers:197: ./drivers/gpu/drm/drm_bridge.c:1521: WARNING: Block quote ends without a blank line; unexpected unindent. [docutils] Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202512302319.1PGGt3CN-lkp@intel.com/ Fixes: 9da0e06abda8 ("drm/bridge: deprecate of_drm_find_bridge()") Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://patch.msgid.link/20251231-drm-bridge-alloc-getput-drm_of_find_bridge-kdoc-fix-v1-1-193a03f0609c@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-01-21dm: fix excessive blk-crypto operations for invalid keysEric Biggers1-9/+3
dm_exec_wrappedkey_op() passes through the derive_sw_secret, import_key, generate_key, and prepare_key blk-crypto operations to an underlying device. Currently, it calls the operation on every underlying device until one returns success. This logic is flawed when the operation is expected to fail, such as an invalid key being passed to derive_sw_secret. That can happen if userspace passes an invalid key to the FS_IOC_ADD_ENCRYPTION_KEY ioctl. When that happens on a device-mapper device that consists of many dm-linear targets, a lot of unnecessary key unwrapping requests get sent to the underlying key wrapping hardware. Fix this by considering the first device only. As already documented in the comment, it was already checked that all underlying devices support wrapped keys, so this should be fine. Fixes: e93912786e50 ("dm: pass through operations on wrapped inline crypto keys") Cc: stable@vger.kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
2026-01-21thermal/drivers/broadcom: Use clamp to simplify bcm2835_thermal_temp2adcThorsten Blum1-6/+2
Use clamp() to simplify bcm2835_thermal_temp2adc() and improve its readability. Explicitly cast BIT() to int to prevent a signedness error. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patch.msgid.link/20260105121308.1761-1-thorsten.blum@linux.dev Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-21Merge tag 'qcom-drivers-for-6.20' of ↵Arnd Bergmann11-168/+1109
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.20 Support multiple wait queues in the SCM firmware interface and provide discovery of the wait queue interrupt to deal with the cases where bootloader didn't patch the DeviceTree with the IRQ information. Refactor the MDT loader and the SCM driver's peripheral authentication service interface and introduce support for passing a remoteproc resource table to the firmware. The remoteproc patches that uses this and uses this to configure the IOMMU are included here due to bidirectional dependencies. The end result is remoteproc support on the Glymur platform. Enable QSEECOM and thereby UEFI variable access, on the Surface Pro 11. Make the QMI interface endianness aware, to support ath1Xk on big endian machines. Add the Glymur support in LLCC driver. * tag 'qcom-drivers-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits) soc: qcom: preserve CPU endianness for QMI_DATA_LEN soc: qcom: fix QMI encoding/decoding for basic elements soc: qcom: check QMI basic element error codes soc: qcom: ubwc: add missing include remoteproc: qcom: pas: Enable Secure PAS support with IOMMU managed by Linux remoteproc: pas: Extend parse_fw callback to fetch resources via SMC call firmware: qcom_scm: Add qcom_scm_pas_get_rsc_table() to get resource table firmware: qcom_scm: Add SHM bridge handling for PAS when running without QHEE firmware: qcom_scm: Refactor qcom_scm_pas_init_image() firmware: qcom_scm: Add a prep version of auth_and_reset function soc: qcom: mdtloader: Remove qcom_mdt_pas_init() from exported symbols soc: qcom: mdtloader: Add PAS context aware qcom_mdt_pas_load() function remoteproc: pas: Replace metadata context with PAS context structure firmware: qcom_scm: Introduce PAS context allocator helper function firmware: qcom_scm: Rename peripheral as pas_id firmware: qcom_scm: Remove redundant piece of code dt-bindings: remoteproc: qcom,pas: Add iommus property soc: qcom: cmd-db: Use devm_memremap() to fix memory leak in cmd_db_dev_probe soc: qcom: pmic_glink_altmode: Consume TBT3/USB4 mode notifications dt-bindings: qcom,pdc: document the Milos Power Domain Controller ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'ti-driver-soc-for-v6.20' of ↵Arnd Bergmann6-51/+34
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers TI SoC driver updates for v6.20 Bug Fixes: - pruss: Fix double free in pruss_clk_mux_setup() - k3-socinfo: Fix regmap leak on probe failure - k3-socinfo: Fix compile testing dependency issue Cleanups: - knav_dma/knav_qmss: Remove redundant ENOMEM printks and simplify error messages - knav_dma/knav: Simplify code with scoped for each OF child loops - ti_sci.h: Fix all kernel-doc warnings * tag 'ti-driver-soc-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: pruss: Fix double free in pruss_clk_mux_setup() soc: ti: k3-socinfo: Fix regmap leak on probe failure soc: ti: k3-socinfo: Fix compile testing soc: ti: knav_dma: Simplify with scoped for each OF child loop soc: ti: knav: Simplify with scoped for each OF child loop soc: ti: knav_dma: Simplify error messages in probe soc: ti: knav_dma: Remove ENOMEM printks soc: ti: knav_qmss: Remove ENOMEM printks firmware: ti_sci.h: fix all kernel-doc warnings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'imx-drivers-6.20' of ↵Arnd Bergmann4-32/+140
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers i.MX drivers changes for 6.20: - A few changes from Peng Fan adding dump syslog support for i.MX System Manager firmware driver, cleaning up soc-imx9 driver, fixing error handling for soc-imx8m driver * tag 'imx-drivers-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx8m: Fix error handling for clk_prepare_enable() soc: imx: Spport i.MX9[4,52] soc: imx: Use dev_err_probe() for i.MX9 soc: imx: Use device-managed APIs for i.MX9 firmware: imx: sm-misc: Dump syslog info firmware: arm_scmi: imx: Support getting syslog of MISC protocol Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'zynqmp-soc-for-6.20' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann2-4/+4
soc/drivers arm64: Xilinx SOC changes for 6.20 - Fix Michal's email in cpuidle driver - s/system_unbound_wq/system_dfl_wq/g in zynqmp_power * tag 'zynqmp-soc-for-6.20' of https://github.com/Xilinx/linux-xlnx: cpuidle: zynq: Switch Michal Simek's email to new one soc/xilinx: replace use of system_unbound_wq with system_dfl_wq Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'tegra-for-6.20-soc' of ↵Arnd Bergmann1-100/+325
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v6.20-rc1 This series primarily refactors the Tegra PMC driver to eliminate reliance on a global variable, transitioning to passing the tegra_pmc context explicitly across clocks, powergates, sysfs/debugfs interfaces, and power management callbacks. Additionally, it resolves a warning during system resume by deferring an unsafe generic_handle_irq() call to a hard IRQ context using irq_work. * tag 'tegra-for-6.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Add PMC contextual functions soc/tegra: pmc: Do not rely on global variable soc/tegra: pmc: Use driver-private data soc/tegra: pmc: Use PMC context embedded in powergates soc/tegra: pmc: Pass PMC context as debugfs data soc/tegra: pmc: Pass PMC context via sys-off callback data soc/tegra: pmc: Embed reboot notifier in PMC context soc/tegra: pmc: Store PMC context in clocks soc/tegra: pmc: Pass struct tegra_pmc to tegra_powergate_state() soc/tegra: pmc: Use contextual data instead of global variable soc/tegra: pmc: Fix unsafe generic_handle_irq() call Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'samsung-drivers-6.20' of ↵Arnd Bergmann1-41/+92
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers Samsung SoC drivers for v6.20 1. Several improvements in Exynos ChipID Socinfo driver and finally adding Google GS101 SoC support. 2. Few cleanups from old code. 3. Documenting Axis Artpec-9 SoC PMU (Power Management Unit). * tag 'samsung-drivers-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: s3c: remove a leftover hwmon-s3c.h header file dt-bindings: soc: samsung: exynos-pmu: Drop unnecessary select schema soc: samsung: exynos-chipid: add google,gs101-otp support soc: samsung: exynos-chipid: downgrade dev_info to dev_dbg for soc info soc: samsung: exynos-chipid: rename method dt-bindings: nvmem: add google,gs101-otp soc: samsung: exynos-chipid: use dev_err_probe where appropiate soc: samsung: exynos-chipid: use devm action to unregister soc device dt-bindings: samsung: exynos-pmu: Add compatible for ARTPEC-9 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'tee-sysfs-for-6.20' of ↵Arnd Bergmann5-18/+144
git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers TEE sysfs for 6.20 - Add an optional generic sysfs attribute for TEE revision - Implement revision reporting for OP-TEE using both SMC and FF-A ABIs * tag 'tee-sysfs-for-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: tee: optee: store OS revision for TEE core tee: add revision sysfs attribute Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'amdtee-update-for-6.20' of ↵Arnd Bergmann1-4/+4
git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers AMDTEE update for 6.20 Remove unused return variables * tag 'amdtee-update-for-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: tee: amdtee: Remove unused return variables Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21thermal/drivers/stm32: Use predefined HZ_PER_MHZ instead of a custom oneAndy Shevchenko1-2/+2
Use predefined HZ_PER_MHZ instead of a custom one. No functional changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260114092808.273695-1-andriy.shevchenko@linux.intel.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-21Merge tag 'tee-bus-callback-for-6.20' of ↵Arnd Bergmann7-115/+144
git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers TEE bus callback for 6.20 - Move from generic device_driver to TEE bus-specific callbacks - Add module_tee_client_driver() and registration helpers to reduce boilerplate - Convert several client drivers (TPM, KEYS, firmware, EFI, hwrng, and RTC) - Update documentation and fix kernel-doc warnings * tag 'tee-bus-callback-for-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: tpm/tpm_ftpm_tee: Fix kdoc after function renames tpm/tpm_ftpm_tee: Make use of tee bus methods tpm/tpm_ftpm_tee: Make use of tee specific driver registration KEYS: trusted: Make use of tee bus methods KEYS: trusted: Migrate to use tee specific driver registration function firmware: tee_bnxt: Make use of tee bus methods firmware: tee_bnxt: Make use of module_tee_client_driver() firmware: arm_scmi: Make use of tee bus methods firmware: arm_scmi: optee: Make use of module_tee_client_driver() efi: stmm: Make use of tee bus methods efi: stmm: Make use of module_tee_client_driver() hwrng: optee - Make use of tee bus methods hwrng: optee - Make use of module_tee_client_driver() rtc: optee: Make use of tee bus methods rtc: optee: Migrate to use tee specific driver registration function tee: Adapt documentation to cover recent additions tee: Add probe, remove and shutdown bus callbacks to tee_client_driver tee: Add some helpers to reduce boilerplate for tee client drivers Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'optee-update-for-6.20' of ↵Arnd Bergmann1-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers OP-TEE update for 6.20 - A micro optimization by making a local array static const - Update OP-TEE mailing list as moderated - Update an outdated comment for cmd_alloc_suppl() * tag 'optee-update-for-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: optee: make read-only array attr static const MAINTAINERS: Mark the OP-TEE mailing list moderated optee: update outdated comment Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'qcomtee-fixes-for-6.20' of ↵Arnd Bergmann3-15/+14
git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers QCOMTEE fixes for 6.20 Small cleanups for the qcomtee driver to align with recommended coding practices for the cleanup.h infrastructure. * tag 'qcomtee-fixes-for-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: tee: qcomtee: user: Fix confusing cleanup.h syntax tee: qcomtee: mem: Fix confusing cleanup.h syntax tee: qcomtee: call: Fix confusing cleanup.h syntax Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'renesas-drivers-for-v6.20-tag2' of ↵Arnd Bergmann8-57/+360
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v6.20 (take two) - Add and use for_each_of_imap_item() iterator, - Add support for the RZ/N1 GPIO Interrupt Multiplexer. * tag 'renesas-drivers-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Add support for RZ/N1 GPIO Interrupt Multiplexer irqchip/renesas-rza1: Use for_each_of_imap_item iterator irqchip/ls-extirq: Use for_each_of_imap_item iterator of: unittest: Add a test case for for_each_of_imap_item iterator of/irq: Introduce for_each_of_imap_item Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-21Merge tag 'scmi-updates-7.0' of ↵Arnd Bergmann17-282/+238
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers Arm SCMI updates for v7.0 A set of cleanups, refactoring, and fixes to the Arm SCMI stack: 1. Rework protocol version negotiation by moving version discovery and downgrade handling into the SCMI core and performing negotiation early, before protocol initialization. Remove legacy per-protocol versioning logic now made redundant by centralized SCMI handling. 2. Increase the internal MAX_OPPS limit in the SCMI performance protocol to 64, allowing platforms with larger OPP tables to be fully supported. 3. Reduce duplicated boilerplate in pinctrl and related protocols by consolidating validation and lookup logic in protocol get info helpers. 4. Refactor reset protocol domain handling by introducing a shared lookup helper, ensuring consistent validation and error reporting. 5. Fix potential undefined behaviour by properly initializing pointers annotated with the __free attribute. * tag 'scmi-updates-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: firmware: arm_scmi: Remove legacy protocol versioning logic firmware: arm_scmi: Rework protocol version negotiation logic firmware: arm_scmi: Increase performance MAX_OPPS limit to 64 firmware: arm_scmi: Move boiler plate code into the get info functions firmware: arm_scmi: Refactor reset domain handling firmware: arm_scmi: Fix uninitialized pointers with __free attr Signed-off-by: Arnd Bergmann <arnd@arndb.de>