aboutsummaryrefslogtreecommitdiff
path: root/drivers/pinctrl
AgeCommit message (Collapse)AuthorFilesLines
2025-02-17pinctrl: cy8c95x0: Get rid of cy8c95x0_pinmux_direction() forward declarationAndy Shevchenko1-29/+25
The function is used before being defined. Just move it up enough to get rid of forward declaration. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-8-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: cy8c95x0: Initialise boolean variable with boolean valuesAndy Shevchenko1-2/+2
The 'ret' variable in cy8c95x0_irq_handler() is defined as bool, but is intialised with integers. Avoid implicit castings and initialise boolean variable with boolean values. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-7-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: cy8c95x0: Replace 'return ret' by 'return 0' in some casesAndy Shevchenko1-3/+3
When it's known that the returned value can't be non-zero, use 'return 0' explicitly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: cy8c95x0: Remove redundant check in cy8c95x0_regmap_update_bits_base()Andy Shevchenko1-11/+5
The function is never called with the PORTSEL register in the argument. Drop unneeded check, but rescue a comment. While at it, drop inline and allow any compiler to choose better stragy (note, that inline in C code is only a recomendation to most of the modern compilers anyway). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: cy8c95x0: Transform to cy8c95x0_regmap_read_bits()Andy Shevchenko1-20/+25
The returned value of cy8c95x0_regmap_read() is used always with a bitmask being applied. Move that bitmasking code into the function. At the same time transform it to cy8c95x0_regmap_read_bits() which will be in align with the write and update counterparts. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: cy8c95x0; Switch to use for_each_set_clump8()Andy Shevchenko1-15/+9
for_each_set_clump8() has embedded check for unset clump to skip. Switch driver to use for_each_set_clump8(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: cy8c95x0: Use better bitmap APIs where appropriateAndy Shevchenko1-21/+12
There are bitmap_gather() and bitmap_scatter() that are factually reimplemented in the driver. Use better bitmap APIs where appropriate. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250205095243.512292-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: mcp23s08: Get rid of spurious level interruptsDmitry Mastykin1-3/+20
irq_mask()/irq_unmask() are not called for nested interrupts. So level interrupts are never masked, chip's interrupt output is not cleared on INTCAP or GPIO read, the irq handler is uselessly called again. Nested irq handler is not called again, because interrupt reason is cleared by its first call. /proc/interrupts shows that number of chip's irqs is greater than number of nested irqs. This patch adds masking and unmasking level interrupts inside irq handler. Signed-off-by: Dmitry Mastykin <mastichi@gmail.com> Link: https://lore.kernel.org/20250122120504.1279790-1-mastichi@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: nuvoton: npcm8xx: Fix error handling in npcm8xx_gpio_fw()Yue Haibing1-2/+2
fwnode_irq_get() was changed to not return 0, fix this by checking for negative error, also update the error log. Fixes: acf4884a5717 ("pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver") Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/20250118031334.243324-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: pistachio: Remove dead code in pistachio_gpio_register()Yue Haibing1-6/+0
fwnode_irq_get() was changed to not return 0, so this check is dead code now. Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20250118031145.243104-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-17pinctrl: devicetree: do not goto err when probing hogs in pinctrl_dt_to_mapValentin Caron1-2/+8
Cross case in pinctrl framework make impossible to an hogged pin and another, not hogged, used within the same device-tree node. For example with this simplified device-tree : &pinctrl { pinctrl_pin_1: pinctrl-pin-1 { pins = "dummy-pinctrl-pin"; }; }; &rtc { pinctrl-names = "default" pinctrl-0 = <&pinctrl_pin_1 &rtc_pin_1> rtc_pin_1: rtc-pin-1 { pins = "dummy-rtc-pin"; }; }; "pinctrl_pin_1" configuration is never set. This produces this path in the code: really_probe() pinctrl_bind_pins() | devm_pinctrl_get() | pinctrl_get() | create_pinctrl() | pinctrl_dt_to_map() | // Hog pin create an abort for all pins of the node | ret = dt_to_map_one_config() | | /* Do not defer probing of hogs (circular loop) */ | | if (np_pctldev == p->dev->of_node) | | return -ENODEV; | if (ret) | goto err | call_driver_probe() stm32_rtc_probe() pinctrl_enable() pinctrl_claim_hogs() create_pinctrl() for_each_maps(maps_node, i, map) // Not hog pin is skipped if (pctldev && strcmp(dev_name(pctldev->dev), map->ctrl_dev_name)) continue; At the first call of create_pinctrl() the hogged pin produces an abort to avoid a defer of hogged pins. All other pin configurations are trashed. At the second call, create_pinctrl is now called with pctldev parameter to get hogs, but in this context only hogs are set. And other pins are skipped. To handle this, do not produce an abort in the first call of create_pinctrl(). Classic pin configuration will be set in pinctrl_bind_pins() context. And the hogged pin configuration will be set in pinctrl_claim_hogs() context. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/20250116170009.2075544-1-valentin.caron@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-14pinctrl: renesas: rza2: Fix potential NULL pointer dereferenceChenyuan Yang1-0/+3
`chip.label` in rza2_gpio_register() could be NULL. Add the missing check. Signed-off-by: Chenyuan Yang <chenyuan0y@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/20250210232552.1545887-1-chenyuan0y@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-14pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/downClaudiu Beznea1-1/+18
The Renesas RZ/G3S supports a power-saving mode where power to most of the SoC components is lost, including the PIN controller. Save and restore the pull-up/pull-down register contents to ensure the functionality is preserved after a suspend/resume cycle. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250205100116.2032765-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-11pinctrl: intel: Fix wrong bypass assignment in intel_pinctrl_probe_pwm()Andy Shevchenko1-1/+0
When instantiating PWM, the bypass should be set to false. The field is used for the selected Intel SoCs that do not have PWM feature enabled in their pin control IPs. Fixes: eb78d3604d6b ("pinctrl: intel: Enumerate PWM device when community has a capability") Reported-by: Alexis GUILLEMET <alexis.guillemet@dunasys.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Alexis GUILLEMET <alexis.guillemet@dunasys.com>
2025-02-06pinctrl: pinconf-generic: Print unsigned value if a format is registeredClaudiu Beznea1-4/+4
Commit 3ba11e684d16 ("pinctrl: pinconf-generic: print hex value") unconditionally switched to printing hex values in pinconf_generic_dump_one(). However, if a dump format is registered for the dumped pin, the hex value is printed as well. This hex value does not necessarily correspond 1:1 with the hardware register value (as noted by commit 3ba11e684d16 ("pinctrl: pinconf-generic: print hex value")). As a result, user-facing output may include information like: output drive strength (0x100 uA). To address this, check if a dump format is registered for the dumped property, and print the unsigned value instead when applicable. Fixes: 3ba11e684d16 ("pinctrl: pinconf-generic: print hex value") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250205101058.2034860-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-03pinctrl: cy8c95x0: Respect IRQ trigger settings from firmwareAndy Shevchenko1-1/+1
Some of the platforms may connect the INT pin via inversion logic effectively make the triggering to be active-low. Remove explicit trigger flag to respect the settings from firmware. Without this change even idling chip produces spurious interrupts and kernel disables the line in the result: irq 33: nobody cared (try booting with the "irqpoll" option) CPU: 0 UID: 0 PID: 125 Comm: irq/33-i2c-INT3 Not tainted 6.12.0-00236-g8b874ed11dae #64 Hardware name: Intel Corp. QUARK/Galileo, BIOS 0x01000900 01/01/2014 ... handlers: [<86e86bea>] irq_default_primary_handler threaded [<d153e44a>] cy8c95x0_irq_handler [pinctrl_cy8c95x0] Disabling IRQ #33 Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250117142304.596106-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-03pinctrl: intel: Import PWM_LPSS namespace for devm_pwm_lpss_probe()Uwe Kleine-König1-0/+1
The Intel pinctrl driver can provide a PWM device and for that needs to call the function devm_pwm_lpss_probe(). That function is provided by the pwm-lpss driver which intends to export it in the "PWM_LPSS" namespace. To prepare fixing the pwm-lpss driver to indeed use the "PWM_LPSS" namespace, import that namespace when used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-02-03pinctrl: cy8c95x0: Rename PWMSEL to SELPWMAndy Shevchenko1-7/+7
There are two registers in the hardware, one, "Select PWM", is per-port configuration enabling PWM function instead of GPIO. The other one is "PWM Select" is per-PWM selector to configure PWM itself. Original code uses abbreviation of the latter to describe the former. Rename it to follow the datasheet. Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250203131506.3318201-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-03pinctrl: cy8c95x0: Enable regmap locking for debugAndy Shevchenko1-0/+4
When regmap locking is disabled, debugfs is also disabled. Enable locking for debug when CONFIG_DEBUG_PINCTRL is set. Fixes: f71aba339a66 ("pinctrl: cy8c95x0: Use single I2C lock") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250203131506.3318201-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-03pinctrl: cy8c95x0: Avoid accessing reserved registersAndy Shevchenko1-6/+10
The checks for vrtual registers in the cy8c95x0_readable_register() and cy8c95x0_writeable_register() are not aligned and broken. Fix that by explicitly avoiding reserved registers to be accessed. Fixes: 71e4001a0455 ("pinctrl: pinctrl-cy8c95x0: Fix regcache") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250203131506.3318201-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-03pinctrl: cy8c95x0: Fix off-by-one in the regmap range settingsAndy Shevchenko1-3/+3
The range_max is inclusive, so we need to use the number of the last accessible register address. Fixes: 8670de9fae49 ("pinctrl: cy8c95x0: Use regmap ranges") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250203131506.3318201-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-03pinctrl: lynxpoint: Use dedicated helpers for chained IRQ handlersAndy Shevchenko1-1/+4
Instead of relying on the fact that the parent IRQ chip supports fasteoi mode and calling the respective callback at the end of the interrupt handler, surround it with enter and exit helpers for chained IRQ handlers which will consider all possible cases. This in particular unifies how GPIO drivers handle IRQ. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-02-03pinctrl: baytrail: Use dedicated helpers for chained IRQ handlersAndy Shevchenko1-1/+4
Instead of relying on the fact that the parent IRQ chip supports fasteoi mode and calling the respective callback at the end of the interrupt handler, surround it with enter and exit helpers for chained IRQ handlers which will consider all possible cases. This in particular unifies how GPIO drivers handle IRQ. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-01-24Merge tag 'pinctrl-v6.14-1' of ↵Linus Torvalds33-146/+3831
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No core changes this time New drivers: - New subdriver for the Qualcomm MSM8917 SoC TLMM - New subdriver for the Mediatek MT7988 SoC - New subdriver for the Rockchip RK3562 SoC - New subdriver for the Renesas RZ/G3E SoC Improvements: - Fix some missing pins in the Qualcomm IPQ5424 TLMM - Fix some missing LVDS pins in the Sunxi A100/A133 - Support Sunxi V853 (simple compatible string) - Cleanups in the Samsung driver - Fix some AMD suspend behaviour - Cleanups" * tag 'pinctrl-v6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (29 commits) dt-bindings: pinctrl: sunxi: add compatible for V853 pinctrl: Use str_enable_disable-like helpers dt-bindings: pinctrl: Correct indentation and style in DTS example pinctrl: amd: Take suspend type into consideration which pins are non-wake pinctrl: stm32: Add check for clk_enable() pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E pinctrl: sunxi: add missed lvds pins for a100/a133 pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd() pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table dt-bindings: pinctrl: renesas: Document RZ/G3E SoC dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H pinctrl: rockchip: add rk3562 support dt-bindings: pinctrl: Add rk3562 pinctrl support pinctrl: Fix the clean up on pinconf_apply_setting failure dt-bindings: pinctrl: add binding for MT7988 SoC pinctrl: mediatek: add MT7988 pinctrl driver pinctrl: mediatek: add support for MTK_PULL_PD_TYPE pinctrl: ocelot: Constify some structures pinctrl: renesas: rzg2l: Add audio clock pins on RZ/G3S ...
2025-01-15pinctrl: Use str_enable_disable-like helpersKrzysztof Kozlowski14-27/+37
Replace ternary (condition ? "enable" : "disable") syntax with helpers from string_choices.h because: 1. Simple function call with one argument is easier to read. Ternary operator has three arguments and with wrapping might lead to quite long code. 2. Is slightly shorter thus also easier to read. 3. It brings uniformity in the text - same string. 4. Allows deduping by the linker, which results in a smaller binary file. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/20250114203602.1013275-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-15Merge tag 'renesas-pinctrl-for-v6.14-tag3' of ↵Linus Walleij1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.14 (take three) - Fix PFC_MASK for RZ/V2H and RZ/G3E. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-14pinctrl: amd: Take suspend type into consideration which pins are non-wakeMaciej S. Szmigiero2-10/+24
Some laptops have pins which are a wake source for S0i3/S3 but which aren't a wake source for S4/S5 and which cause issues when left unmasked during hibernation (S4). For example HP EliteBook 855 G7 has pin #24 that causes instant wakeup (hibernation failure) if left unmasked (it is a wake source only for S0i3/S3). GPIO pin #24 on this platform is likely dedicated to WWAN XMM7360 modem since this pin triggers wake notify to WWAN modem's parent PCIe port. Fix this by considering a pin a wake source only if it is marked as one for the current suspend type (S0i3/S3 vs S4/S5). Since Z-wake pins only make sense at runtime these were excluded from both of suspend categories, so pins with only the Z-wake flag set are effectively treated as non-wake pins. Fixes: 2fff0b5e1a6b ("pinctrl: amd: Mask non-wake source pins with interrupt enabled at suspend") Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/d4b2d076366fdd08a0c1cd9b7ecd91dc95e07269.1736184752.git.mail@maciej.szmigiero.name Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-14pinctrl: stm32: Add check for clk_enable()Mingwei Zheng1-38/+38
Convert the driver to clk_bulk*() API. Add check for the return value of clk_bulk_enable() to catch the potential error. Fixes: 05d8af449d93 ("pinctrl: stm32: Keep pinctrl block clock enabled when LEVEL IRQ requested") Signed-off-by: Mingwei Zheng <zmw12306@gmail.com> Signed-off-by: Jiasheng Jiang <jiashengjiangcool@gmail.com> Reviewed-by: Antonio Borneo <antonio.borneo@foss.st.com> Link: https://lore.kernel.org/20250106220659.2640365-1-zmw12306@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-14Merge tag 'renesas-pinctrl-for-v6.14-tag2' of ↵Linus Walleij2-6/+181
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.14 (take two) - Add support for alpha-numerical port references on the RZ/V2H SoC, - Add support for the RZ/G3E (R9A09G047) Soc. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-14pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3ELad Prabhakar1-1/+1
The PFC_MASK value for the PFC_mx registers is currently hardcoded to 0x07, which is correct for SoCs in the RZ/G2L family, but insufficient for RZ/V2H and RZ/G3E, where the mask value should be 0x0f. This discrepancy causes incorrect PFC register configuration on RZ/V2H and RZ/G3E SoCs. On RZ/G2L, the PFC_mx bitfields are also 4 bits wide, with bit 4 marked as reserved. The reserved bits are documented to read as zero and be ignored when written. Updating the PFC_MASK definition from 0x07 to 0x0f ensures compatibility with both SoC families while maintaining correct behavior on RZ/G2L. Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250110221045.594596-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-13pinctrl: sunxi: add missed lvds pins for a100/a133Parthiban Nallathambi1-0/+12
lvds, lcd, dsi all shares the same GPIO D bank and lvds0 data 3 lines and lvds1 pins are missed, add them. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Link: https://lore.kernel.org/20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-08pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd()Linus Walleij1-18/+0
This function is unused and causing compile errors, delete it. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-01-03pinctrl: renesas: rzg2l: Add support for RZ/G3E SoCBiju Das2-0/+174
Add pinctrl driver support for RZ/G3E SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216195325.164212-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-03pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg tableBiju Das1-6/+7
Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg table with alpha-numeric port names to match with the hardware manual. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216195325.164212-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-03Merge tag 'pinctrl-v6.13-2' of ↵Linus Torvalds1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - A small Kconfig fixup for the i.MX. In principle this could come in from the SoC tree but the bug was introduced from the pin control tree so let's fix it from here. - Fix a sleep in atomic context in the MCP23xxx GPIO expander by disabling the regmap locking and using explicit mutex locks. * tag 'pinctrl-v6.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: mcp23s08: Fix sleeping in atomic context due to regmap locking ARM: imx: Re-introduce the PINCTRL selection
2025-01-03Merge tag 'samsung-pinctrl-6.14' of ↵Linus Walleij2-3/+4
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.14 Two fixes for very old issues around error handling and also one cleanup. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-27pinctrl: rockchip: add rk3562 supportSteven Liu2-3/+200
Add support for the 5 GPIO banks in the rk3562. Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/20241224093620.3815705-1-kever.yang@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-27pinctrl: Fix the clean up on pinconf_apply_setting failureMukesh Ojha1-20/+30
When some client does devm_pinctrl_get() followed by pinctrl_select_state() that does pinmux first successfully and later during config setting it sets the wrong drive strenght to the pin due to which pinconf_apply_setting fails. Currently, on failure during config setting is implemented as if pinmux has failed for one of the pin but that does not seem right and need to undo the pinmux for all the pin if config setting fails. Current commit does a bit refactor to reuse the code and tries to clean up mux setting on config setting failure. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://lore.kernel.org/20241224084441.515870-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-27pinctrl: mediatek: add MT7988 pinctrl driverDaniel Golle3-0/+1564
Add pinctrl driver for the MediaTek MT7988 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> [correctly initialise for the function_desc structure] Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/20241217085435.9586-3-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-27pinctrl: mediatek: add support for MTK_PULL_PD_TYPEDaniel Golle2-11/+63
The MediaTek MT7988 SoC got some pins which only got configurable pull-down but unlike previous designs there is no pull-up option. Add new type MTK_PULL_PD_TYPE to support configuring such pins. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-20pinctrl: ocelot: Constify some structuresChristophe JAILLET1-10/+10
'struct ocelot_match_data and 'struct irq_chip' are not modified in this driver. Constifying these structures moves some data to a read-only section, so increase overall security, especially when the structure holds some function pointers. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 41459 9008 80 50547 c573 drivers/pinctrl/pinctrl-ocelot.o After: ===== text data bss dec hex filename 42803 7640 80 50523 c55b drivers/pinctrl/pinctrl-ocelot.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/32edcf0567fffd0b1a219e7e2dad7e0bd8c5aaf4.1734023550.git.christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-20Merge tag 'renesas-pinctrl-for-v6.14-tag1' of ↵Linus Walleij1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.14 - Add audio clock pin support for the RZ/G3S SoC. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-20pinctrl: renesas: rzg2l: Add audio clock pins on RZ/G3SClaudiu Beznea1-0/+2
Add audio clock pins on the RZ/G3S SoC. These are used by audio IPs as input pins to feed them with audio clocks. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241113133540.2005850-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-17pinctrl: mcp23s08: Fix sleeping in atomic context due to regmap lockingEvgenii Shatokhin1-0/+6
If a device uses MCP23xxx IO expander to receive IRQs, the following bug can happen: BUG: sleeping function called from invalid context at kernel/locking/mutex.c:283 in_atomic(): 1, irqs_disabled(): 1, non_block: 0, ... preempt_count: 1, expected: 0 ... Call Trace: ... __might_resched+0x104/0x10e __might_sleep+0x3e/0x62 mutex_lock+0x20/0x4c regmap_lock_mutex+0x10/0x18 regmap_update_bits_base+0x2c/0x66 mcp23s08_irq_set_type+0x1ae/0x1d6 __irq_set_trigger+0x56/0x172 __setup_irq+0x1e6/0x646 request_threaded_irq+0xb6/0x160 ... We observed the problem while experimenting with a touchscreen driver which used MCP23017 IO expander (I2C). The regmap in the pinctrl-mcp23s08 driver uses a mutex for protection from concurrent accesses, which is the default for regmaps without .fast_io, .disable_locking, etc. mcp23s08_irq_set_type() calls regmap_update_bits_base(), and the latter locks the mutex. However, __setup_irq() locks desc->lock spinlock before calling these functions. As a result, the system tries to lock the mutex whole holding the spinlock. It seems, the internal regmap locks are not needed in this driver at all. mcp->lock seems to protect the regmap from concurrent accesses already, except, probably, in mcp_pinconf_get/set. mcp23s08_irq_set_type() and mcp23s08_irq_mask/unmask() are called under chip_bus_lock(), which calls mcp23s08_irq_bus_lock(). The latter takes mcp->lock and enables regmap caching, so that the potentially slow I2C accesses are deferred until chip_bus_unlock(). The accesses to the regmap from mcp23s08_probe_one() do not need additional locking. In all remaining places where the regmap is accessed, except mcp_pinconf_get/set(), the driver already takes mcp->lock. This patch adds locking in mcp_pinconf_get/set() and disables internal locking in the regmap config. Among other things, it fixes the sleeping in atomic context described above. Fixes: 8f38910ba4f6 ("pinctrl: mcp23s08: switch to regmap caching") Cc: stable@vger.kernel.org Signed-off-by: Evgenii Shatokhin <e.shatokhin@yadro.com> Link: https://lore.kernel.org/20241209074659.1442898-1-e.shatokhin@yadro.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-17pinctrl: nomadik: Add check for clk_enable()Mingwei Zheng1-7/+28
Add check for the return value of clk_enable() to catch the potential error. Disable success clks in the error handling. Change return type of nmk_gpio_glitch_slpm_init casade. Fixes: 3a19805920f1 ("pinctrl: nomadik: move all Nomadik drivers to subdir") Signed-off-by: Mingwei Zheng <zmw12306@gmail.com> Signed-off-by: Jiasheng Jiang <jiashengjiangcool@gmail.com> Link: https://lore.kernel.org/20241206221618.3453159-1-zmw12306@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-17pinctrl: ingenic: Replace seq_printf() by seq_puts()Geert Uytterhoeven1-1/+1
Simplify "seq_printf(p, "%s", ...)" to "seq_puts(p, ...)". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9a5b38027ed674ca773fe28a3b3246631eae8834.1733404358.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-17pinctrl: qcom: ipq5424: split spi0 pin groupManikanta Mylavarapu1-8/+26
The GPIO configuration differs for the spi0 clk, cs, miso, mosi pins. Therefore, split the spi0 pin group and assign function to each pin as per the specification. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/20241217091308.3253897-3-quic_mmanikan@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-16pinctrl: qcom: Add MSM8917 tlmm pinctrl driverOtto Pflüger3-0/+1627
It is based on MSM8916 driver with the pinctrl definitions from Qualcomm's downstream MSM8917 driver. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/20241215-msm8917-v9-3-bacaa26f3eef@mainlining.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra24-34/+34
Clean up the existing export namespace code along the same lines of commit 33def8498fdd ("treewide: Convert macro and uses of __section(foo) to __section("foo")") and for the same reason, it is not desired for the namespace argument to be a macro expansion itself. Scripted using git grep -l -e MODULE_IMPORT_NS -e EXPORT_SYMBOL_NS | while read file; do awk -i inplace ' /^#define EXPORT_SYMBOL_NS/ { gsub(/__stringify\(ns\)/, "ns"); print; next; } /^#define MODULE_IMPORT_NS/ { gsub(/__stringify\(ns\)/, "ns"); print; next; } /MODULE_IMPORT_NS/ { $0 = gensub(/MODULE_IMPORT_NS\(([^)]*)\)/, "MODULE_IMPORT_NS(\"\\1\")", "g"); } /EXPORT_SYMBOL_NS/ { if ($0 ~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+),/) { if ($0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/ && $0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(\)/ && $0 !~ /^my/) { getline line; gsub(/[[:space:]]*\\$/, ""); gsub(/[[:space:]]/, "", line); $0 = $0 " " line; } $0 = gensub(/(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/, "\\1(\\2, \"\\3\")", "g"); } } { print }' $file; done Requested-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://mail.google.com/mail/u/2/#inbox/FMfcgzQXKWgMmjdFwwdsfgxzKpVHWPlc Acked-by: Greg KH <gregkh@linuxfoundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-12-02pinctrl: samsung: update child reference drop commentJavier Carrasco1-1/+1
Commit 954445c72fc7 ("pinctrl: samsung: Drop redundant node parameter in samsung_banks_of_node_get()") modified the name of the function used to release child nodes from samsung_drop_banks_of_node() to samsung_banks_node_put(). Update the comment to use the current function name. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20241106-samsung-pinctrl-put-v1-2-de854e26dd03@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit