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2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal3-0/+80
Program in the steps for Non TBT PLL disable sequence. The whole function can be defined in one shot since most of prequiste functions are already coded in. Bspec: 74492 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-17-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal3-2/+32
Program the rest of the LT Phy Non TBT PLL Enable sequence. This can be done in a single patch since the rest of the prequistie functions are already coded in. Bspec: 74492, 69701 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal2-0/+26
Program the rest of the steps with regards to PORT_CLOCK_CTL in Non-TBT PLL enable sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-15-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal5-5/+143
Program the LT PHY P2P transaction which uses P2M cycle to get get data fro Phy when it is ready and then go read the MAC register from the MAC address space. Bspec: 68966, 74497, 74483, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-14-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal3-0/+97
Create a reverse algorithm which is used to find port clock from the LT PHY state is provided which is used for comparision & verification functions. Bspec: 74667 Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-13-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal1-0/+26
We enable SSC when we program PORT_CLOCK_CTL register. We logically determine if ssc is enabled or not while we calculate our state. Bspec: 74492, 74667 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal1-0/+4
When we get the eDP tables we reuse dp tables for some data rates. We need to modify the 3rd config value of this table to 1 instead of 0 since that is the only difference in the dp and edp table for that particular data rate. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-11-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal3-5/+45
Fetch the tables which need to be used and program it in the specified VDR register space. Everything is done over the respective lanes. Bspec: 68862, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal4-1/+1036
Add the LT Phy programming recipe tables for eDP, DP & HDMI and a function to use the correct table. Bspec: 74667 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal3-25/+123
Read PHY_VDR_0_CONFIG to check if there is any change in the register and decide based on that if P2P sequence to change the data rate of LT PHY are required or not. This scenario only happens if the requested mode uses 1.62Gbps with DP mode since LT PHY defaults to this mode if any other mode is requested we need to follow the whole sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal3-3/+18
Add a wrapper on cx0 powerdown change sequence for LT Phy usage, as the sequence remains unchanged when going from SNPS Phy to LT Phy. Bspec: 74495 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal2-0/+38
Program sequence from port clock ctl except for the SSC enablement part which will be taken care of later. Bspec: 74492 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-6-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Move the HDMI FRL function to intel_hdmiSuraj Kandpal3-18/+18
Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and make it non static. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-5-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal8-1/+202
Define function to bring phy lane out of reset for LT Phy and the corresponding pre-requisite steps before we follow the steps for Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence function in which we can place this function Bspec: 77449, 74749, 74499, 74495, 68960 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Change register bit naming for powerdown valuesSuraj Kandpal2-12/+12
Change the register bit naming for powerdown values from CX0 to XELPDP so that it can be used with LT Phy too. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-3-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add LT Phy related VDR and Pipe RegistersSuraj Kandpal1-0/+24
Add LT Phy related VDR and pipe registers into its own new file. Bspec: 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-2-suraj.kandpal@intel.com
2025-10-31Merge tag 'amd-drm-next-6.19-2025-10-29' of ↵Simona Vetter256-892/+3549
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-10-29: amdgpu: - VPE idle handler fix - Re-enable DM idle optimizations - DCN3.0 fix - SMU fix - Powerplay fixes for fiji/iceland - License copy-pasta fixes - HDP eDP panel fix - Vblank fix - RAS fixes - SR-IOV updates - SMU 13 VCN reset fix - DMUB fixes - DC frame limit fix - Additional DC underflow logging - DCN 3.1.5 fixes - DC Analog encoders support - Enable DC on bonaire by default - UserQ fixes - Remove redundant pm_runtime_mark_last_busy() calls amdkfd: - Process cleanup fix - Misc fixes radeon: - devm migration fixes - Remove redundant pm_runtime_mark_last_busy() calls UAPI - Add ABM KMS property Proposed kwin changes: https://invent.kde.org/plasma/kwin/-/merge_requests/6028 Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251029205713.9480-1-alexander.deucher@amd.com
2025-10-31drm/xe/pf: Allow to stop the VF using sysfsMichal Wajdeczko1-0/+49
It is expected that VFs activity will be monitored and in some cases admin might want to silence specific VF without killing the VM where it was attached. Add write-only attribute to stop GuC scheduling at VFs level. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── vf1/ │ └── stop [WO] bool ├── vf2/ │ └── stop [WO] bool Writing "1" or "y" (or whatever is recognized by the strtobool() function) to this file will trigger the change of the VF state to STOP (GuC will stop servicing the VF). To go back to a READY state (to allow GuC to service this VF again) the VF FLR must be triggered (which can be done by writing 1 to device/reset file). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-17-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add sysfs device symlinks to enabled VFsMichal Wajdeczko3-0/+101
For convenience, for every enabled VF add 'device' symlink from our SR-IOV admin VF folder to enabled sysfs PCI VF device entry. Remove all those links when disabling PCI VFs. For completeness, add static 'device' symlink for the PF itself. /sys/bus/pci/drivers/xe/BDF/sriov_admin/ ├── pf │   └── device -> ../../../BDF # PF BDF ├── vf1 │   └── device -> ../../../BDF' # VF1 BDF ├── vf2 │   └── device -> ../../../BDF" # VF2 BDF Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-16-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Promote xe_pci_sriov_get_vf_pdevMichal Wajdeczko2-13/+24
In the upcoming patch we would like to use this private helper during preparation of the sysfs links. Promote it. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-15-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow change PF scheduling priority using sysfsMichal Wajdeczko1-2/+82
We have just added bulk change of the scheduling priority for all VFs and PF, but that only allow to select LOW and NORMAL priority. Add read-write attribute under PF to allow changing its priority without impacting other VFs priority settings. For completeness also add read-only attributes under VFs, to show currently selected priority levels used by the VFs. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ │ └── profile │ └── sched_priority [RW] low, normal, high ├── vf1/ │ └── profile │ └── sched_priority [RO] low, normal Writing "high" to the PF read-write attribute will change PF priority on all tiles/GTs to HIGH (schedule function in the next time-slice after current one completes and it has work). Writing "low" or "normal" to change priority to LOW/NORMAL is supported. When read, those files will display the current and available scheduling priorities. The currently active priority level will be enclosed in square brackets, default output will be like: $ grep . -h sriov_admin/{pf,vf1,vf2}/profile/sched_priority [low] normal high [low] normal [low] normal Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-14-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow bulk change all VFs priority using sysfsMichal Wajdeczko1-1/+41
It is expected to be a common practice to configure the same level of scheduling priority across all VFs and PF (at least as starting point). Due to current GuC FW limitations it is also the only way to change VFs priority. Add write-only sysfs attribute that will apply required priority level to all VFs and PF at once. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── .bulk_profile │   └── sched_priority [WO] low, normal Writing "low" to this write-only attribute will change PF and VFs scheduling priority on all tiles/GTs to LOW (function will be scheduled only if it has work submitted). Similarly, writing "normal" will change functions priority to NORMAL (functions will be scheduled irrespective of whether there is a work or not). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-13-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to provision scheduling priorityMichal Wajdeczko2-0/+97
We already have function to configure PF (or VF) scheduling priority on a single GT, but we also need function that will cover all tiles and GTs. However, due to the current GuC FW limitation, we can't always rely on per-GT function as it actually only works for the PF case. The only way to change VFs scheduling priority is to use 'sched_if_idle' policy KLV that will change priorities for all VFs (and the PF). We will use these new functions in the upcoming patches. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-12-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow bulk change all VFs EQ/PT using sysfsMichal Wajdeczko1-0/+36
It is expected to be a common practice to configure the same values of execution quantum and preemption timeout parameters across all VFs. Add write-only sysfs attributes that will apply required EQ/PT values globally, without forcing admin to update PF and each VF separately. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── .bulk_profile │   ├── exec_quantum_ms [WO] unsigned integer │   └── preempt_timeout_us [WO] unsigned integer Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-11-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to bulk provision EQ/PTMichal Wajdeczko2-0/+58
We already have functions to configure EQ/PT for single VF across all tiles/GTs. Now add helper functions that will do that for all VFs (and the PF) at once. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-10-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to bulk configure EQ/PT on GTMichal Wajdeczko2-0/+58
We already have functions to bulk configure 'hard' resources like GGTT, LMEM or GuC context/doorbells IDs. Now add functions for the 'soft' scheduling parameters, as we will need them soon in the upcoming patches. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-9-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Fix signature of internal config helpersMichal Wajdeczko1-2/+2
Both pf_get_exec_quantum() and pf_get_preempt_timeout() should return u32 as this is a type of the underlying data. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-8-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Relax report helper to accept PF in bulk configsMichal Wajdeczko1-5/+8
Our current bulk configuration requests are only about VFs, but we want to add new functions that will also include PF configs. Update our bulk report helper to accept also PFID as first VFID. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-7-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow change PF and VFs EQ/PT using sysfsMichal Wajdeczko3-2/+195
On current platforms, in SR-IOV virtualization, the GPU is shared between VFs on the time-slice basis. The 'execution quantum' (EQ) and 'preemption timeout' (PT) are two main scheduling parameters that could be set individually per each VF. Add EQ/PT read-write attributes for the PF and all VFs. By exposing those two parameters over sysfs, the admin can change their default values (infinity) and let the GuC scheduler enforce that settings. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ │ └── profile │ ├── exec_quantum_ms [RW] unsigned integer │ └── preempt_timeout_us [RW] unsigned integer ├── vf1/ │ └── profile │ ├── exec_quantum_ms [RW] unsigned integer │ └── preempt_timeout_us [RW] unsigned integer Writing 0 to these files will set infinity EQ/PT for the VF on all tiles/GTs. This is a default value. Writing non-zero integers to these files will change EQ/PT to new value (in their respective units: msec or usec). Reading from these files will return EQ/PT as previously set on all tiles/GTs. In case of inconsistent values detected, due to errors or low-level configuration done using debugfs, -EUCLEAN error will be returned. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-6-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add _locked variants of the VF PT config functionsMichal Wajdeczko2-17/+52
In upcoming patches we will want to configure VF's preemption timeout (PT) on all GTs under single lock to avoid potential races due to parallel GT configuration attempts. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-5-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add _locked variants of the VF EQ config functionsMichal Wajdeczko2-17/+53
In upcoming patches we will want to configure VF's execution quantum (EQ) on all GTs under single lock to avoid potential races in parallel GT configuration attempts. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-4-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Take RPM during calls to SR-IOV attr.store()Michal Wajdeczko1-2/+14
We expect that all SR-IOV attr.store() handlers will require active runtime PM reference. To simplify implementation of those handlers, take an implicit RPM reference on their behalf. Also wait until PF completes its restart. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-3-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Prepare sysfs for SR-IOV admin attributesMichal Wajdeczko5-0/+317
We already have some SR-IOV specific knobs exposed as debugfs files to allow low level tuning of the SR-IOV configurations, but those files are mainly for the use by the developers and debugfs might not be available on the production builds. Start building dedicated sysfs sub-tree under xe device, where in upcoming patches we will add selected attributes that will help provision and manage PF and all VFs: /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ ├── vf1/ ├── vf2/ : └── vfN/ Add all required data types and helper macros that will be used by upcoming patches to define actual attributes. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-2-michal.wajdeczko@intel.com
2025-10-31Merge tag 'drm-xe-fixes-2025-10-30' of ↵Simona Vetter2-11/+16
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Driver Changes: - Fix xe_validation_guard() not guarding (Thomas Hellström) - Do not wake device during a GT reset (Matthew Brost) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/o2b3lucyitafbbcd5bewpfqnslavtnnpc6ck4qatnou2wwukix@rz6seyfw75uy
2025-10-31Merge tag 'drm-misc-fixes-2025-10-30' of ↵Simona Vetter8-22/+43
https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Short summary of fixes pull: ast: - Preserve correct bits on register I/O dma-fence: - Use correct timeline name etnaviv: - Use correct GPU adress space for flush imx: - parallel-display: Fix bridge handling nouveau: - Fix locking in scheduler panel: - kingdisplay-kd097d04: Disable EOT packet - sitronix-st7789v: Use correct SYNC flags sched: - Fix locking to avoid race condition - Fix SIGKILL handling sysfb: - Avoid NULL-pointer access Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251030195644.GA188441@localhost.localdomain
2025-10-31Merge tag 'drm-intel-fixes-2025-10-30' of ↵Simona Vetter1-1/+54
https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes - Fix DMC/DC6 asserts on ADL-S (Ville) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/aQNtTV75vPaDhnXh@intel.com
2025-10-31Merge tag 'drm-msm-fixes-2025-10-29' of ↵Simona Vetter15-43/+59
https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.18-rc4 CI - Disable broken sanity job GEM - Fix vm_bind prealloc error path - Fix dma-buf import free - Fix last-fence update - Reject MAP_NULL if PRR is unsupported - Ensure vm is created in VM_BIND ioctl GPU - GMU fw parsing fix DPU: - Fixed mode_valid callback - Fixed planes on DPU 1.x devices. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV03kUm1ms7FBg0m9U4ZcyickSWbnayAWqYqs0XH4UjWf+A@mail.gmail.com
2025-10-31Merge tag 'amd-drm-fixes-6.18-2025-10-29' of ↵Simona Vetter14-40/+61
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.18-2025-10-29: amdgpu: - VPE idle handler fix - Re-enable DM idle optimizations - DCN3.0 fix - SMU fix - Powerplay fixes for fiji/iceland - License fixes - HDP eDP panel fix - Vblank fix radeon: - devm migration fixes Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251029201342.8813-1-alexander.deucher@amd.com
2025-10-31Merge tag 'drm-intel-gt-next-2025-10-29' of ↵Simona Vetter4-7/+17
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Driver Changes: Fixes/improvements/new stuff: - Set O_LARGEFILE in __create_shmem() (Taotao Chen) - Fix incorrect error handling in shmem_pwrite() (Taotao Chen) - Skip GuC communication warning on reset in progress [guc] (Zhanjun Dong) - Fix conversion between clock ticks and nanoseconds [guc] (Umesh Nerlige Ramappa) Miscellaneous: - Avoid accessing uninitialized context in emit_rpcs_query() [selftests] (Krzysztof Karas) - Fix typo in comment (I915_EXEC_NO_RELOC) [gem] (Marlon Henrique Sanches) Backmerges: - Merge drm/drm-next into drm-intel-gt-next (Joonas Lahtinen) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Tvrtko Ursulin <tursulin@igalia.com> Link: https://patch.msgid.link/aQH994lQI_iVPzTI@linux
2025-10-31Merge tag 'mediatek-drm-fixes-20251028' of ↵Simona Vetter1-10/+0
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes Mediatek DRM Fixes - 20251028 1. Fix device use-after-free on unbind Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patch.msgid.link/20251028151548.3944-1-chunkuang.hu@kernel.org
2025-10-31Merge tag 'drm-misc-next-2025-10-28' of ↵Simona Vetter31-66/+1044
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.19-rc1: UAPI Changes: Cross-subsystem Changes: - Update DT bindings for renesas and powervr-rogue. - Update MAINTAINERS email and add spsc_queue. Core Changes: - Allow ttm page protection flags on risc-v. - Move freeing of drm client memory to driver. Driver Changes: - Assorted small fixes and updates to qaic, ivpu, st7571-i2c, gud, amdxdna. - Allow configuration of vkms' display through configfs. - Add Arm Ethos-U65/U85 accel driver. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/32b43261-3c99-49d9-92ee-615ada1d01e8@lankhorst.se
2025-10-31Merge tag 'drm-xe-next-2025-10-28' of ↵Simona Vetter62-216/+530
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next Driver Changes: More xe3p support (Harish, Brian, Balasubramani, Matt Roper) Make panic support work on VRAM for display (Maarten) Fix stolen size check (Shuicheng) xe_pci_test update (Gustavo) VF migration updates (Tomasz) A couple of fixes around allocation and PM references (Matt Brost) Migration update for the MEM_COPY instruction (Matt Auld) Initial CRI support (Balasubramani, Matt Roper) Use SVM range helpers in PT layer (Matt Brost) Drop MAX_GT_TYPE_CHARS constant (Matt Roper) Fix spelling and typos (Sanjay) Fix VF FLR synchronization between all GTs (Michal) Add a Workaround (Nitin) Access VF's register using dedicated MMIO view (Michal) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> Link: https://patch.msgid.link/aQCl9uJxN6CWJ8Vg@fedora
2025-10-31Merge tag 'amd-drm-next-6.19-2025-10-24' of ↵Simona Vetter215-1446/+21768
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-10-24: amdgpu: - HMM cleanup - Add new RAS framework - DML2.1 updates - YCbCr420 fixes - DC FP fixes - DMUB fixes - LTTPR fixes - DTBCLK fixes - DMU cursor offload handling - Userq validation improvements - Misc code cleanups - Unify shutdown callback handling - Suspend improvements - Power limit code cleanup - Fence cleanup - IP Discovery cleanup - SR-IOV fixes - AUX backlight fixes - DCN 3.5 fixes - HDMI compliance fixes - DCN 4.0.1 cursor updates - DCN interrupt fix - DC KMS full update improvements - Add additional HDCP traces - DCN 3.2 fixes - DP MST fixes - Add support for new SR-IOV mailbox interface Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20251024175249.58099-1-alexander.deucher@amd.com
2025-10-31drm/xe/xe3: Extend wa_14023061436Tangudu Tilak Tirumalesh1-0/+2
Extend wa_14023061436 to Graphics Versions 30.03, 30.04 and 30.05. Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251030154626.3124565-1-tilak.tirumalesh.tangudu@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-10-31drm/xe: highlight reserved PAT entries in dump outputXin Wang2-7/+13
Enhance the PAT table dump by marking reserved entries with an asterisk (*) for improved readability and debugging. V2: Added a note in the "PAT table" header explaining the meaning of the asterisk(*) to improve clarity for readers. (Matt Roper) V3: Introduced a valid field in struct xe_pat_table_entry to explicitly track whether an entry is valid or reserved, avoiding reliance on coh_mode == 0. (Matt Roper) Signed-off-by: Xin Wang <x.wang@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251030221734.1058350-1-x.wang@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-10-31drm/tidss: Set vblank (event) time at crtc_atomic_enableTomi Valkeinen1-2/+7
It was reported that Weston stops at an assert, which checks that the page flip event timestamp is the same or newer than the previous timestamp: weston_output_finish_frame: Assertion `timespec_sub_to_nsec(stamp, &output->frame_time) >= 0' failed. With manual tests, I can see that when I enable the CRTC, I get a page flip event with a timestamp of 0. Tracking this down led to drm_reset_vblank_timestamp() which does "t_vblank = 0" if "high-precision query" is not available. TI DSS does not have any hardware timestamping, and thus the default ktime_get() is used in the DRM framework to get the vblank timestamp, and ktime_get() is not "high precision" here. It is not quite clear why the framework behaves this way, but I assume the idea is that drm_crtc_vblank_on(), which calls drm_reset_vblank_timestamp(), can be called at any time, and thus ktime_get() wouldn't give a good timestamp. And, the idea is that the driver would wait until next vblank after the CRTC enable, and then we could get a good timestamp. This is hinted in the comment: "reinitialize delayed at next vblank interrupt and assign 0 for now". I think that makes sense. However, when we enable the CRTC in TI DSS, i.e. we write the enable bit to the hardware, that's the exact moment when the "vblank cycle" starts. It is the zero point in the cycle, and thus ktime_get() would give a good timestamp. I am not sure if this is applicable to other hardware, and if so, how should it be solved in the framework. So, let's fix this in the tidss driver at least for now. This patch updates the vblank->time manually to ktime_get() just before sending the vblank event, and we enable the crtc just before calling ktime_get(). To get even more exact timing, the dispc_vp_enable() is moved inside the event_lock spinlock. With this, we get a proper timestamp for the page flip event from enabling the CRTC, and Weston is happy. Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-2-c2aedf31e2c9@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Closes: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1553964/processor-sdk-am62x-weston-fails-to-wake-from-idle-time-sleep-restarts-after-sigterm Closes: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1416342/am625-am625-doesn-t-wake-up-from-standy-when-idle-time-is-configured-in-weston-ini
2025-10-31drm/tidss: Restructure dispc_vp_prepare() and dispc_vp_enable()Tomi Valkeinen3-19/+8
tidss_crtc.c calls dispc_vp_prepare() and dispc_vp_enable() in that order, next to each other. dispc_vp_prepare() does preparations for enabling the crtc, by writing some registers, and dispc_vp_enable() does more preparations. As the last thing, dispc_vp_enable() enables the CRTC by writing the enable bit. There might have been a reason at some point in the history for this split, but I can't find any point to it. They also do a bit of overlapping work: both call dispc_vp_find_bus_fmt(). They could as well be a single function. But instead of combining them, this patch moves everything from dispc_vp_enable() to dispc_vp_prepare(), except the actual CRTC enable bit write. The reason for this is that unlike all the preparatory register writes, CRTC enable has an immediate effect, starting the timing generator and the CRTC as a whole. Thus it may be important to time the enable just right (as we do in the next patch). No functional changes. Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-1-c2aedf31e2c9@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-10-31drm/sched: Add warning for removing hack in drm_sched_fini()Philipp Stanner1-1/+8
The assembled developers agreed at the X.Org Developers Conference 2025 that the hack added for amdgpu in drm_sched_fini() shall be removed. It shouldn't be needed by amdgpu anymore. As it's unclear whether all drivers really follow the life time rule of entities having to be torn down before their scheduler, it is reasonable to warn for a while before removing the hack. Add a warning in drm_sched_fini() that fires if an entity is still active. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20251023123429.139848-2-phasta@kernel.org
2025-10-31drm/imagination: Fix reference to devm_platform_get_and_ioremap_resource()Geert Uytterhoeven1-1/+1
The call to devm_platform_ioremap_resource() was replaced by a call to devm_platform_get_and_ioremap_resource(), but the comment referring to the function's possible returned error codes was not updated. Fixes: 927f3e0253c11276 ("drm/imagination: Implement MIPS firmware processor and MMU support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://patch.msgid.link/2266514318480d17f52c7e5e67578dae6827914e.1761745586.git.geert+renesas@glider.be Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-10-31drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBCVinod Govindapillai4-17/+71
There is a hw restriction that we could enable the FBC for FP16 formats only if the pixel normalization block is enabled. Hence enable the pixel normalizer block with normalzation factor as 1.0 for the supported FP16 formats to get the FBC enabled. Two existing helper function definitions are moved up to avoid the forward declarations as part of this patch as well. v2: sw/hw state differentiation on handling pixel normalizer (Jani) Bspec: 69863, 68881 Cc: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251027134001.325064-5-vinod.govindapillai@intel.com
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