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2025-12-10drm/amdgpu: Init compute partition mode for gfx v12_1Hawking Zhang1-6/+28
Init compute partition mode for gfx v12_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Initialize memory ranges for gmc v12_1Hawking Zhang1-0/+8
Initialize memory ranges for gmc v12_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Initialize memory partition callbacks for gmc v12_1Hawking Zhang1-0/+2
Initialize memory partition callbacks for gmv v12_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: support rlc autoload for muti-xccLikun Gao1-19/+38
Support rlc autload for muti-xcc on gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Enable atomics for all the available xccHawking Zhang1-5/+14
Apply TCP_UTCL0_CNTL1 settings to all the available xcc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Update MES VM_CNTX_CNTL for XNACK off for GFX 12.1Mukul Joshi5-6/+14
Currently, we do not turn off retry faults in VM_CONTEXT_CNTL value when passing it to MES if XNACK is off. This creates a situation where XNACK is disabled in SQ but enabled in UTCL2, which is not recommended. As a result, turn off/on retry faults in both SQ and UTCL2 when passing vm_context_cntl value to MES if XNACK is disabled/enabled. Suggested-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdkfd: Enable per-process XNACK for GFX 12.1.0Mukul Joshi5-2/+8
GFX 12.1.0 will support enabling/disabling XNACK on a per- process basis. This change enables the per process XNACK feature. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Enable retry faults for GFX 12.1Mukul Joshi2-1/+5
Enable retry faults in both GCVM/MMVM Context1 Control and L2_PROTECTION_FAULT_CNTL2 registers for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add IH node-id to XCC mappingMukul Joshi1-4/+29
Add a generic function to map IH node-id to XCC instance. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add interrupt handler for GFX 12.1.0Mukul Joshi4-3/+224
Add a separate interrupt handler for handling interrupts, both retry and no-retry, for GFX 12.1.0. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add UTCL2 Retry fault interrupt for GFX 12.1Mukul Joshi2-2/+19
Add the UTCL2 retry fault interrupt for both GCVM and MMVM for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/sdma: add query for CSA size and alignmentAlex Deucher3-0/+31
Needed to query the CSA size and alignment for SDMA user queues. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: fix mes packet params issue when flush hdp.chong li10-114/+160
v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li <chongli2@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/gfx: add eop size and alignment to shadow infoAlex Deucher3-0/+10
This is used by firmware for compute user queues. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amd/ras: Add vram_type to ras_ta_init_flagsCandice Li4-0/+4
Add vram_type to ras_ta_init_flags. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: update sdma configuration for soc v1_0Likun Gao1-0/+4
Update SDMA instances/masks according to xcc num for multi-xcc models on soc v1.0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Initialize xcp manager for soc v1_0Hawking Zhang1-0/+25
Initialize xcp manager for soc v1_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add soc_v1_0_xcp_funcsHawking Zhang1-0/+411
Implement xcp mgr callbacks for soc v1_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Export sdma_v7_1_xcp_funcsHawking Zhang1-0/+1
To be used by soc v1_0 xcp manager Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Export gfx_v12_1_xcp_funcHawking Zhang1-0/+2
To be used by soc v1_0 xcp manager Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add vram_type to ras init_flagsCandice Li2-0/+2
Add vram_type to ras init_flags. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amd/ras: Reduce stack usage in amdgpu_virt_ras_get_cper_records()Srinivasan Shanmugam1-4/+13
amdgpu_virt_ras_get_cper_records() was using a large stack array of ras_log_info pointers. This contributed to the frame size warning on this function. Replace the fixed-size stack array: struct ras_log_info *trace[MAX_RECORD_PER_BATCH]; with a heap-allocated array using kcalloc(). We free the trace buffer together with out_buf on all exit paths. If allocation of trace or out_buf fails, we return a generic RAS error code. This reduces stack usage and keeps the runtime behaviour unchanged. Fixes: stack frame size: 1112 bytes (limit: 1024) Cc: Tao Zhou <tao.zhou1@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdkfd: Handle GPU reset and drain retry fault racePhilip Yang1-1/+6
Only check and drain IH1 ring if CAM is not enabled. If GPU is under reset, don't access IH to drain retry fault. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10Revert "drm/amd/display: Fix pbn to kbps Conversion"Mario Limonciello1-23/+36
Deeply daisy chained DP/MST displays are no longer able to light up. This reverts commit e0dec00f3d05 ("drm/amd/display: Fix pbn to kbps Conversion") Cc: Jerry Zuo <jerry.zuo@amd.com> Reported-by: nat@nullable.se Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4756 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add switch_compute_partition callback for imu v12_1Hawking Zhang2-0/+21
To enable switching compute partition mode v2: cleanup (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Implement gfx_v12_1_get_xccs_per_xcpHawking Zhang1-0/+7
Use gfx v12_1 callback to query the numbers of xccs per xcp v2: add todo (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Remove redundant check for async_gfx_ringHawking Zhang1-3/+1
Remove the redundant check for async_gfx_ring, as it is not required for gfx v12_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: disable graphics doorbell range for gfx v12_1Likun Gao1-0/+4
Disable doorbell range for graphics engine on gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: enable unmap doorbell handle for gfx v12_1Likun Gao1-1/+1
Enable unmapped doorbell handling for gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: revision doorbel range for gfx v12_1Likun Gao1-16/+6
Revision doorbell range on muti-XCC mode for gfx v12_1. Clean up doorbell range set for graphics engine. V2: Remove doorbell range set from gfx_v12_1_xcc_kiq_init_register. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdkfd: disable shader message vgpr deallocation on gc 12.1Jonathan Kim1-0/+5
Shader messages to deallocate VGPRs prior to shader end can prevent the trap handler from saving context, making debugging and core dumps unreliable. VGPR deallocations for performance gain is negligible. GC 12.1 will NOP shader VGPR deallocation messages via HW settings on driver boot. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Acked-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Remove redundant pmfw backdoor loadingHawking Zhang1-15/+0
PMFW is integrated into ifwi for gfx 12_1 adapter, making PMFW backdoor loading unnecessary. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amd: Fix unbind/rebind for VCN 4.0.5Mario Limonciello (AMD)1-0/+2
Unbinding amdgpu has no problems, but binding it again leads to an error of sysfs file already existing. This is because it wasn't actually cleaned up on unbind. Add the missing cleanup step. Fixes: 547aad32edac ("drm/amdgpu: add VCN4 ip block support") Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/acpi: Reduce amdgpu_acpi_detect stack usageSrinivasan Shanmugam1-5/+10
amdgpu_acpi_detect() calls some helper functions it calls have large local structures. When the compiler inlines these helpers, their local data adds to the amdgpu_acpi_detect() stack frame. Mark the helpers with noinline_for_stack: - amdgpu_atif_verify_interface() - amdgpu_atif_get_notification_params() - amdgpu_atif_query_backlight_caps() - amdgpu_atcs_verify_interface() - amdgpu_acpi_enumerate_xcc() This keeps the large temporary objects inside the helper’s own stack frame instead of being inlined into the caller, preventing the caller from growing beyond the stack limit. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:1403:6: warning: stack frame size (1688) exceeds limit (1024) in 'amdgpu_acpi_detect' [-Wframe-larger-than] Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/xe/guc: Recommend GuC v70.54.0 for BMG, PTLJulia Filipchuk1-2/+2
UAPI compatibility version 1.27.0 Update recommended GuC version for BMG, PTL. Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20251125014134.2075988-15-julia.filipchuk@intel.com
2025-12-10drm/xe/guc: Recommend GuC v70.53.0 for MTL, DG2, LNLJulia Filipchuk1-3/+3
UAPI compatibility version 1.26.0 Update recommended GuC version for MTL, DG2, LNL. Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20251125014134.2075988-14-julia.filipchuk@intel.com
2025-12-10drm/i915: Fix BO alloc flagsLoïc Molinari1-0/+1
I915_BO_ALLOC_NOTHP must be added to the I915_BO_ALLOC_FLAGS mask in order to pass GEM_BUG_ON() valid flags checks. v2: - Add Tvrtko's A-b Reported-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Closes: https://lore.kernel.org/intel-gfx/d73adfa8-d61b-46b3-9385-dde53d8db8ad@intel.com/ Fixes: a8a9a590221c ("drm/i915: Use huge tmpfs mountpoint helpers") Suggested-by: Tvrtko Ursulin <tursulin@ursulin.net> Signed-off-by: Loïc Molinari <loic.molinari@collabora.com> Acked-by: Tvrtko Ursulin <tursulin@ursulin.net> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20251210143617.712808-1-loic.molinari@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-10drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug messageImre Deak1-5/+7
On C10 PHY PLLs the SSC is enabled by programming the XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the PHY_C10_VDR_PLL 4..8 registers: - If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the PHY_C10_VDR_PLL registers are programmed to non-zero values. - If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the PHY_C10_VDR_PLL registers are programmed to zeroed-out values. The driver's state checker verifies if the above settings are consistent, i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to the PHY_C10_VDR_PLL registers being zeroed-out or not. On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8 registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This will trigger the following PLL state check warning during driver loading: <4>[ 44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled) <4>[ 44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281 intel_cx0pll_readout_hw_state+0x221/0x620 [xe] It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just ignores them in this case. Since the driver always programs the register values according to the above, it still makes sense to verify that the programming happened correctly. To avoid the state check WARN during driver loading due to the way BIOS programs the registers, convert the WARN to a debug message. While at it clarify the debug message. v2: Clarify the debug message. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251209153407.1791839-1-imre.deak@intel.com
2025-12-10drm/gem: Fix builds with CONFIG_MMU=nBoris Brezillon1-0/+2
drm_gem_get_unmapped_area() relies on mm_get_unmapped_area() which is only available if CONFIG_MMU=y. Fixes: 99bda20d6d4c ("drm/gem: Introduce drm_gem_get_unmapped_area() fop") Cc: Loïc Molinari <loic.molinari@collabora.com> Reviewed-by: Loïc Molinari <loic.molinari@collabora.com> Link: https://patch.msgid.link/20251209171151.2449120-1-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-10drm/i915/psr: Allow async flip when Selective Fetch enabledJouni Högander1-8/+0
Now as Selective Fetch is performing full frame update on async flip and vblank evasion is done as needed we can allow async flip even when Selective Fetch is enabled. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251204070718.1090778-4-jouni.hogander@intel.com
2025-12-10drm/i915/psr: Perform full frame update on async flipJouni Högander1-1/+2
According to bspec selective fetch is not supported with async flips and instructing full frame update on async flip. v4: - check crtc_state->async_flip_planes in psr2_sel_fetch_pipe_state_supported v3: - rebase - fix old_crtc_state->pipe_srcsz_early_tpt - fix using intel_atomic_get_new_crtc_state v2: - check also crtc_state->async_flip_planes in psr2_sel_fetch_plane_state_supported Bspec: 55229 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251204070718.1090778-3-jouni.hogander@intel.com
2025-12-10drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSRJouni Högander1-4/+6
Currently plane id bit is set in crtc_state->async_flip_planes only when async flip toggle workaround is needed. We want to utilize crtc_state->async_flip_planes further in Selective Fetch calculation. v2: - rework if-else if to if-if - added comment updated Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251204070718.1090778-2-jouni.hogander@intel.com
2025-12-10drm/{i915, xe}/stolen: make insert_node, area_address, area_size optionalJani Nikula2-27/+10
Since the stolen memory hooks are function pointers, make some of them optional instead of having to define them for xe. insert_node, area_address, and area_size are only needed on platforms not supported by xe. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/0dbb460e8bd1df29df98862d08fcdfda03912673.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/{i915, xe}/stolen: move stolen memory handling to display parent interfaceJani Nikula10-130/+202
Call the stolen memory interface through the display parent interface. This makes xe compat gem/i915_gem_stolen.h redundant, and it can be removed. v2: Rebase, convert one more call that appeared Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/350c82c49fe40f6319d14d309180e2e2752145ac.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/xe/stolen: unify interface with i915Jani Nikula2-4/+4
Have i915_gem_stolen_node_offset() return u64, and pass const pointer to them. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/e1ae0c5d3cc6f59d6e4f4ce810a6e9b3870109f8.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/i915/fbc: let to_intel_display() do its generic magicJani Nikula1-17/+17
to_intel_display() generics can handle struct intel_plane_state, struct intel_atomic_state, and struct intel_crtc just fine. Pass them directly. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/14d0979eea358fb3713640eae74a7a8801cd8eec.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/Kconfig: sort driver Kconfig source listJani Nikula1-112/+50
Sort the driver Kconfig source list, and remove the superfluous blank lines in between. Reviewed-by: Louis Chauvet <louis.chauvet@bootlin.com> Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/4fa11ab0b938d5c726b6ad78d28c7527b830f696.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/Kconfig: move generic Kconfig options above driversJani Nikula1-12/+12
Keep non-driver options together, above drivers. DRM_PANEL_ORIENTATION_QUIRKS remains alone at the end because it's outside of the whole "if DRM" block. Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/a0f9e1a31a2190f535f2c2f94af6e22030db199f.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/vgem: move Kconfig under driver directoryJani Nikula2-8/+10
Almost all DRM driver Kconfig options are in dedicated Kconfig files under driver directories. Follow suit in vgem. Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/51935bfb299e8c64beae5a654d908231e2ec9c7f.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/hyperv: move Kconfig under driver directoryJani Nikula2-13/+15
Almost all DRM driver Kconfig options are in dedicated Kconfig files under driver directories. Follow suit in hyperv. Cc: Deepak Rawat <drawat.floss@gmail.com> Reviewed-by: Deepak Rawat <drawat.floss@gmail.com> Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/4923196ab968bfdbcc2d7572d9be9886c32c06c9.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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