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2026-01-13drm/panel: simple: restore connector_type fallbackLudovic Desroches1-45/+44
The switch from devm_kzalloc() + drm_panel_init() to devm_drm_panel_alloc() introduced a regression. Several panel descriptors do not set connector_type. For those panels, panel_simple_probe() used to compute a connector type (currently DPI as a fallback) and pass that value to drm_panel_init(). After the conversion to devm_drm_panel_alloc(), the call unconditionally used desc->connector_type instead, ignoring the computed fallback and potentially passing DRM_MODE_CONNECTOR_Unknown, which drm_panel_bridge_add() does not allow. Move the connector_type validation / fallback logic before the devm_drm_panel_alloc() call and pass the computed connector_type to devm_drm_panel_alloc(), so panels without an explicit connector_type once again get the DPI default. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Fixes: de04bb0089a9 ("drm/panel/panel-simple: Use the new allocation in place of devm_kzalloc()") Cc: stable@vger.kernel.org Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://lore.kernel.org/stable/20251126-lcd_panel_connector_type_fix-v2-1-c15835d1f7cb%40microchip.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251218-lcd_panel_connector_type_fix-v3-1-ddcea6d8d7ef@microchip.com
2026-01-13drm/panel-simple: fix connector type for DataImage SCF0700C48GGU18 panelMarek Vasut1-0/+1
The connector type for the DataImage SCF0700C48GGU18 panel is missing and devm_drm_panel_bridge_add() requires connector type to be set. This leads to a warning and a backtrace in the kernel log and panel does not work: " WARNING: CPU: 3 PID: 38 at drivers/gpu/drm/bridge/panel.c:379 devm_drm_of_get_bridge+0xac/0xb8 " The warning is triggered by a check for valid connector type in devm_drm_panel_bridge_add(). If there is no valid connector type set for a panel, the warning is printed and panel is not added. Fill in the missing connector type to fix the warning and make the panel operational once again. Cc: stable@vger.kernel.org Fixes: 97ceb1fb08b6 ("drm/panel: simple: Add support for DataImage SCF0700C48GGU18") Signed-off-by: Marek Vasut <marex@nabladev.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260110152750.73848-1-marex@nabladev.com
2026-01-13drm/panel: himax-hx83102: change to gpiod_set_value_cansleepVladimir Yakovlev1-6/+6
It's better to use gpiod_set_value_cansleep because the panel can be connected via i2c/spi expander or similar external devices for reference see Documentation/driver-api/gpio/consumer.rst Signed-off-by: Vladimir Yakovlev <vovchkir@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251208161613.3763049-1-vovchkir@gmail.com
2026-01-13drm/panel: mantix: Don't turn on MIPI peripheralSebastian Krzyszkowiak1-2/+0
It's not necessary with these panels. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260105-mantix-halo-fixes-v1-5-1ebc9b195a34@puri.sm
2026-01-13drm/panel: mantix: Drop bank 9 initializationSebastian Krzyszkowiak1-4/+2
This command is part of LIC sequence included in FT8006P firmware. There's no need to repeat it here. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260105-mantix-halo-fixes-v1-4-1ebc9b195a34@puri.sm
2026-01-13drm/panel: mantix: Improve power off sequenceSebastian Krzyszkowiak1-4/+8
According to the sequence from section 7.3.4 of FT8006P datasheet, TP_RSTN and RESX should be asserted after disabling AVDD and AVEE and together with VDDI. Also, AVEE power down needs to happen at least 150ms after entering sleep mode. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260105-mantix-halo-fixes-v1-3-1ebc9b195a34@puri.sm
2026-01-13drm/panel: mantix: Improve power on sequence timingsSebastian Krzyszkowiak1-6/+7
FP8006P datasheet mentions: > It is necessary to wait 15msec after releasing RESX before sending > commands. Also Sleep Out command cannot be sent for 120 msec. This hasn't been respected by the driver so far, which could interfere with the LCD init code sequence performed by the controller. In some cases this leads to VCOM voltage being set to a wrong value, causing "halo" effects, temporary burn-in around the edges of the screen and degraded image contrast. T3 and T4 are counted from when VDDI is enabled. There's no need to add them when we've already waited more than that in T2 and T2d. While FT8006P datasheet does not mention a delay between exiting sleep mode and turning the display on, code provided by the vendor uses 120ms there and it happens to be the same value as required in newer datasheets for newer controllers from the same family, so it seems appropriate to use it here as well. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260105-mantix-halo-fixes-v1-2-1ebc9b195a34@puri.sm
2026-01-13drm/panel: mantix: Enable DSI LPMSebastian Krzyszkowiak1-1/+1
This improves reliability of sending DSI commands. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260105-mantix-halo-fixes-v1-1-1ebc9b195a34@puri.sm
2026-01-13drm/panel: Fix a possible null-pointer dereference in jdi_panel_dsi_remove()Tuo Li1-1/+3
In jdi_panel_dsi_remove(), jdi is explicitly checked, indicating that it may be NULL: if (!jdi) mipi_dsi_detach(dsi); However, when jdi is NULL, the function does not return and continues by calling jdi_panel_disable(): err = jdi_panel_disable(&jdi->base); Inside jdi_panel_disable(), jdi is dereferenced unconditionally, which can lead to a NULL-pointer dereference: struct jdi_panel *jdi = to_panel_jdi(panel); backlight_disable(jdi->backlight); To prevent such a potential NULL-pointer dereference, return early from jdi_panel_dsi_remove() when jdi is NULL. Signed-off-by: Tuo Li <islituo@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251218120955.11185-1-islituo@gmail.com
2026-01-13drm/panel: simple: Add Innolux G150XGE-L05 panel entryFabio Estevam1-0/+29
Add support for the Innolux G150XGE-L05 15.0" TFT 1024x768 LVDS panel. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260102141706.36842-2-festevam@gmail.com
2026-01-13drm/panel: ilitek-ili9882t: Switch Tianma TL121BVMS07 to DSC 120Hz modeLangyan Ye1-11/+136
Migrate the TL121BVMS07 panel from non-DSC 60 Hz to DSC-enabled 120 Hz, including updated init sequence, DSC configuration, and display timings. Signed-off-by: Langyan Ye <yelangyan@huaqin.corp-partner.google.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251216075530.1966327-1-yelangyan@huaqin.corp-partner.google.com
2026-01-13drm/msm/dsi_phy_14nm: convert from divider_round_rate() to ↵Brian Masney1-6/+1
divider_determine_rate() The divider_round_rate() function is now deprecated, so let's migrate to divider_determine_rate() instead so that this deprecated API can be removed. Note that when the main function itself was migrated to use determine_rate, this was mistakenly converted to: req->rate = divider_round_rate(...) This is invalid in the case when an error occurs since it can set the rate to a negative value. Fixes: cc41f29a6b04 ("drm/msm/dsi_phy_14nm: convert from round_rate() to determine_rate()") Signed-off-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/697613/ Link: https://lore.kernel.org/r/20260108-clk-divider-round-rate-v1-24-535a3ed73bf3@redhat.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/mdp5: drop support for MSM8998, SDM630 and SDM660Dmitry Baryshkov2-317/+13
Currently MDP5 3.x (MSM8998, SDM630 and SDM660) platforms are support by both DPU and MDP5 drivers. Support for them in the DPU driver is mature enough, so it's no longer sensible to keep them enabled in the MDP5 driver. Not to mention that MSM8998 never used an MDP5 compatible string. Drop support for the MDP5 3.x genration inside the MDP5 driver and migrate those to the DPU driver only. Note: this will break if one uses the DT generated before v6.3 as they had only the generic, "qcom,mdp5" compatible string for SDM630 and SDM660. However granted that we had two LTS releases inbetween I don't think it is an issue. Patchwork: https://patchwork.freedesktop.org/patch/696491/ Link: https://lore.kernel.org/r/20251228-mdp5-drop-dpu3-v4-3-7497c3d39179@oss.qualcomm.com Tested-by: Alexey Minnekhanov <alexeymin@minlexx.ru> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/dpu: fix CMD panels on DPU 1.x - 3.xDmitry Baryshkov1-3/+4
DPU units before 4.x don't have a separate CTL_START IRQ to mark the begin of the data transfer. In such a case, wait for the frame transfer to complete rather than trying to wait for the CTL_START interrupt (and obviously hitting the timeout). Fixes: 050770cbbd26 ("drm/msm/dpu: Fix timeout issues on command mode panels") Reported-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Closes: https://lore.kernel.org/r/8e1d33ff-d902-4ae9-9162-e00d17a5e6d1@postmarketos.org Patchwork: https://patchwork.freedesktop.org/patch/696490/ Link: https://lore.kernel.org/r/20251228-mdp5-drop-dpu3-v4-2-7497c3d39179@oss.qualcomm.com Tested-by: Alexey Minnekhanov <alexeymin@minlexx.ru> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/dpu: drop intr_start from DPU 3.x catalog filesDmitry Baryshkov3-15/+0
DPU 3.x don't have separate intr_start interrupt, drop it from catalog files. Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms") Patchwork: https://patchwork.freedesktop.org/patch/696488/ Link: https://lore.kernel.org/r/20251228-mdp5-drop-dpu3-v4-1-7497c3d39179@oss.qualcomm.com Tested-by: Alexey Minnekhanov <alexeymin@minlexx.ru> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/dpu: use standard functions in _dpu_format_populate_plane_sizes_ubwc()Dmitry Baryshkov1-36/+27
The _dpu_format_populate_plane_sizes_ubwc() used MSM_MEDIA_ALIGN() and MSM_MEDIA_ROUNDUP(), macros inherited from the previous implementation, msm_media_info.h. Replace them with the standard Linux macros, round_up() and DIV_ROUND_UP() respectively. Patchwork: https://patchwork.freedesktop.org/patch/688182/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-12-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/dpu: rewrite _dpu_format_populate_plane_sizes_ubwc()Dmitry Baryshkov2-1219/+57
Drop extra wrapping layer (msm_media_info.h) and inline all VENUS_*() functions, simplifying the code. Patchwork: https://patchwork.freedesktop.org/patch/688184/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-11-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/dpu: drop redundant num_planes assignment in ↵Dmitry Baryshkov1-8/+3
_dpu_format_populate_plane_sizes*() Drop redundant layout->num_planes assignments, using the value assigned from the formats table. RGB UBWC formats need special handling: they use two planes (per the format table), but the uAPI defines plane[1] as empty. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688180/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-10-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/dpu: simplify _dpu_format_populate_plane_sizes_*Dmitry Baryshkov1-22/+19
Move common bits of _dpu_format_populate_plane_sizes_ubwc() and _linear() to dpu_format_populate_plane_sizes(), reducing unnecessary duplication and simplifying code flow fror the UBWC function. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688178/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-9-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: drop PSEUDO_YUV_FMT_LOOSE_TILEDDmitry Baryshkov1-20/+0
Drop PSEUDO_YUV_FMT_LOOSE_TILED(), the macro is unused. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688176/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-8-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: pull in common tiled YUV format parametersDmitry Baryshkov1-15/+13
Pull common params of tiled YUV formats into corresponding macro definitions, simplifying format table. Patchwork: https://patchwork.freedesktop.org/patch/688174/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-7-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: pull in common YUV format parametersDmitry Baryshkov1-64/+56
Pull common params of YUV formats into corresponding macro definitions, simplifying format table. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688171/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-6-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: simplify tiled RGB{,A,X} formats definitionsDmitry Baryshkov1-33/+85
Define several additional macros, capturing tiled RGB format classes, in order to simplify defining particular RGB* format. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688169/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-5-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: simplify RGB{,A,X} formats definitionsDmitry Baryshkov1-117/+158
Define several additional macros, capturing RGB format classes, in order to simplify defining particular RGB* format. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688168/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-4-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: set num_planes, fetch_mode and tile_height in ↵Dmitry Baryshkov1-22/+13
INTERLEAVED_RGB_FMT_TILED All interleaved compressed RGB formats use only 2 planes, MDP_FETCH_LINEAR and MDP_TILE_HEIGHT_UBWC. Specify num_planes, fetch_mode and tile_height directly in the macro and remove unused parameters. Patchwork: https://patchwork.freedesktop.org/patch/688166/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-3-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: set num_planes and fetch_mode in INTERLEAVED_RGB_FMTDmitry Baryshkov1-75/+39
All interleaved RGB formats use only 1 plane and MDP_FETCH_LINEAR. Specify num_planes and fetch_mode directly in the macro and remove unused parameters. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688163/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-2-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-13drm/msm/disp: set num_planes to 1 for interleaved YUV formatsDmitry Baryshkov1-4/+4
Interleaved YUV formats use only one plane for all pixel data. Specify num_planes = 1 for those formats. This was left unnoticed since _dpu_format_populate_plane_sizes_linear() overrides layout->num_planes. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688162/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-1-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-12drm/i915/guc: Recommend GuC v70.53.0 for DG2, MTLJulia Filipchuk1-2/+2
UAPI compatibility version 1.26.0 Update recommended GuC version for DG2, MTL. Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patch.msgid.link/20251112182606.1470733-2-julia.filipchuk@intel.com
2026-01-12drm/xe/hwmon: Expose individual VRAM channel temperatureKarthik Poosa2-0/+69
Expose individual VRAM temperature attributes. Update Xe hwmon documentation for this entry. v2: - Avoid using default switch case for VRAM individual temperatures. - Append labels with VRAM channel number. - Update kernel version in Xe hwmon documentation. v3: - Add missing brackets in Xe hwmon documentation from VRAM channel sysfs. - Reorder BMG_VRAM_TEMPERATURE_N macro in xe_pcode_regs.h. - Add api to check if VRAM is available on the channel. v4: - Improve VRAM label handling to eliminate temp variable by introducing a dedicated array vram_label in xe_hwmon_thermal_info. - Remove a magic number. - Change the label from vram_X to vram_ch_X. v5: - Address review comments from Raag. - Change vram to VRAM in commit title and subject. - Refactor BMG_VRAM_TEMPERATURE_N macro. - Refactor is_vram_ch_available(). - Rephrase a comment. - Check individual VRAM temperature limits in addition to VRAM availability in xe_hwmon_temp_is_visible. (Raag) - Move VRAM label change out of this patch. v6: - Use in_range() for VRAM_N index check instead of if check. (Raag) - Minor aesthetic changes. Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260112203521.1014388-5-karthik.poosa@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-01-12drm/xe/hwmon: Expose GPU PCIe temperatureKarthik Poosa2-0/+34
Expose GPU PCIe average temperature and its limits via hwmon sysfs entry temp5_xxx. Update Xe hwmon sysfs documentation for this. v2: Update kernel version in Xe hwmon documentation. (Raag) v3: - Address review comments from Raag. - Remove redundant debug log. - Update kernel version in Xe hwmon documentation. (Raag) v4: - Address review comments from Raag. - Group new temperature attributes with existing temperature attributes as per channel index in Xe hwmon documentation. - Use TEMP_MASK instead of TEMP_MASK_MAILBOX. - Add PCIE_SENSOR_MASK which uses REG_FIELD_GET as replacement of PCIE_SENSOR_SHIFT. v5: - Address review comments from Raag. - Use REG_FIELD_GET to get PCIe temperature. - Move PCIE_SENSOR_GROUP_ID and PCIE_SENSOR_MASK to xe_pcode_api.h - Cosmetic change. Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260112203521.1014388-4-karthik.poosa@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-01-12drm/xe/hwmon: Expose memory controller temperatureKarthik Poosa2-5/+76
Expose GPU memory controller average temperature and its limits under temp4_xxx. Update Xe hwmon documentation for this. v2: - Rephrase commit message. (Badal) - Update kernel version in Xe hwmon documentation. (Raag) v3: - Update kernel version in Xe hwmon documentation. - Address review comments from Raag. - Remove obvious comments. - Remove redundant debug logs. - Remove unnecessary checks. - Avoid magic numbers. - Add new comments. - Use temperature sensors count to make memory controller visible. - Use temperature limits of package for memory controller. v4: - Address review comments from Raag. - Group new temperature attributes with existing temperature attributes as per channel index in Xe hwmon documentation. - Use DIV_ROUND_UP to calculate dwords needed for temperature limits. - Minor aesthetic refinements. - Remove unused TEMP_MASK_MAILBOX. v5: - Use REG_FIELD_GET to get count from READ_THERMAL_DATA output. (Raag) - Change count print from decimal to hexadecimal. - Cosmetic changes. Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260112203521.1014388-3-karthik.poosa@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-01-12drm/xe/hwmon: Expose temperature limitsKarthik Poosa5-3/+108
Read temperature limits using pcode mailbox and expose shutdown temperature limit as tempX_emergency, critical temperature limit as tempX_crit and GPU max temperature limit as temp2_max. Update Xe hwmon documentation with above entries. v2: - Resolve a documentation warning. - Address below review comments from Raag. - Update date and kernel version in Xe hwmon documentation. - Remove explicit disable of has_mbx_thermal_info for unsupported platforms. - Remove unnecessary default case in switches. - Remove obvious comments. - Use TEMP_LIMIT_MAX to compute number of dwords needed in xe_hwmon_thermal_info. - Remove THERMAL_LIMITS_DWORDS macro. - Use has_mbx_thermal_info for checking thermal mailbox support. v3: - Address below minor comments. (Raag) - Group new temperature attributes with existing temperature attributes as per channel index in Xe hwmon documentation. - Rename enums of xe_temp_limit to improve clarity. - Use DIV_ROUND_UP to calculate dwords needed for temperature limits. - Use return instead of breaks in xe_hwmon_temp_read. - Minor aesthetic refinements. v4: - Remove a redundant break. (Raag) - Update drm_dbg to drm_warn to inform user of unavailability for thermal mailbox on expected platforms. Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260112203521.1014388-2-karthik.poosa@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-01-12drm/xe/ptl: Enable PXP for PTLDaniele Ceraolo Spurio1-0/+1
Now that the GSC FW is defined, we can enable PXP for PTL. The feature will only be turned on if the binary is found on disk. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260108011340.2562349-8-daniele.ceraolospurio@intel.com
2026-01-12drm/xe/ptl: Define GSC for PTLDaniele Ceraolo Spurio1-0/+1
PTL is identified by GSC major version 105. The compatibility version is still 1.0. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com> Link: https://patch.msgid.link/20260108011340.2562349-7-daniele.ceraolospurio@intel.com
2026-01-12drm/xe/gsc: Make GSC FW load optional for newer platformsDaniele Ceraolo Spurio3-10/+15
On newer platforms GSC FW is only required for content protection features, so the core driver features work perfectly fine without it (and we did in fact not enable it to start with on PTL). Therefore, we can selectively enable the GSC only if the FW is found on disk, without failing if it is not found. Note that this means that the FW can now be enabled (i.e., we're looking for it) but not available (i.e., we haven't found it), so checks on FW support should use the latter state to decide whether to go on or not. As part of the rework, the message for FW not found has been cleaned up to be more readable. While at it, drop the comment about xe_uc_fw_init() since the code has been reworked and the statement no longer applies. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com> Link: https://patch.msgid.link/20260108011340.2562349-6-daniele.ceraolospurio@intel.com
2026-01-12drm/xe/device: Convert wait for lmem init into an assertBalasubramani Vivekanandan1-57/+16
Prior to lmem init check, driver is waiting for the pcode uncore_init status. uncore_init status will be flagged after the complete boot and initialization of the SoC by the pcode. uncore_init confirms that lmem init and mmio unblock has been already completed. It makes no sense to check for lmem init after the pcode uncore_init check. So change the wait for lmem init check into an assert which confirms lmem init is set. Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251219145024.2955946-2-balasubramani.vivekanandan@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-01-12drm/xe: Privatize xe_ggtt_nodeMaarten Lankhorst2-18/+19
Nothing requires it any more, make the member private. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/20260108101014.579906-16-dev@lankhorst.se
2026-01-12drm/xe: Improve xe_gt_sriov_pf_config GGTT handlingMaarten Lankhorst3-7/+20
Do not directly dereference xe_ggtt_node, and add a function to retrieve the allocated GGTT size. Reviewed-by: Matthew.brost@intel.com Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/20260108101014.579906-15-dev@lankhorst.se
2026-01-12drm/xe: Do not dereference ggtt_node in xe_bo.cMaarten Lankhorst1-3/+3
A careful inspection of __xe_ggtt_insert_bo_at() shows that the ggtt_node can always be seen as inserted from xe_bo.c due to the way error handling is performed. The checks are also a little bit too paranoid, since we never create a bo with ggtt_node[id] initialised but not inserted into the GGTT, which can be seen by looking at __xe_ggtt_insert_bo_at() Additionally, the size of the GGTT is never bigger than 4 GB, so adding a check at that level is incorrect. Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260108101014.579906-14-dev@lankhorst.se
2026-01-12drm/xe/display: Avoid dereferencing xe_ggtt_nodeMaarten Lankhorst3-5/+5
Start using xe_ggtt_node_addr, and avoid comparing the base offset as vma->node is dynamically allocated. Also sneak in a xe_bo_size() for stolen, too small to put as separate commit. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260108101014.579906-13-dev@lankhorst.se
2026-01-12drm/xe: Add xe_ggtt_node_addr() to avoid dereferencing xe_ggtt_nodeMaarten Lankhorst3-3/+18
This function makes it possible to add an offset that is applied to all xe_ggtt_node's, and hides the internals from all its users. Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260108101014.579906-12-dev@lankhorst.se
2026-01-12drm/xe: Convert xe_fb_pin to use a callback for insertion into GGTTMaarten Lankhorst4-81/+131
The rotation details belong in xe_fb_pin.c, while the operations involving GGTT belong to xe_ggtt.c. As directly locking xe_ggtt etc results in exposing all of xe_ggtt details anyway, create a special function that allocates a ggtt_node, and allow display to populate it using a callback as a compromise. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/20260108101014.579906-11-dev@lankhorst.se
2026-01-12drm/xe: Start using ggtt->start in preparation of balloon removalMaarten Lankhorst5-34/+60
Instead of having ggtt->size point to the end of ggtt, have ggtt->size be the actual size of the GGTT, and introduce ggtt->start to point to the beginning of GGTT. This will allow a massive cleanup of GGTT in case of SRIOV-VF. Reviewed-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/20260108101014.579906-10-dev@lankhorst.se
2026-01-12drm/xe/mert: Move MERT initialization to xe_mert.cMichal Wajdeczko3-3/+15
Most of the MERT code is already in dedicated file, no reason to keep internal MERT data structure initialization elsewhere. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260109151219.26206-6-michal.wajdeczko@intel.com
2026-01-12drm/xe/mert: Use local mert variable to simplify the codeMichal Wajdeczko1-5/+6
There is no need to always refer to MERT data using tile pointer. Use of local mert pointer will simplify the code and make it look like other existing MERT function. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260109151219.26206-5-michal.wajdeczko@intel.com
2026-01-12drm/xe/mert: Always refer to MERT using xe_deviceMichal Wajdeczko3-8/+6
There is only one MERT instance and while it is located on the root tile, it is safer to refer to it using xe_device rather than xe_tile. This will also allow to align signature with other MERT function. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260111213847.27869-1-michal.wajdeczko@intel.com
2026-01-12drm/xe/mert: Fix kernel-doc for struct xe_mertMichal Wajdeczko1-1/+4
Add simple top level kernel-doc for the struct itself to allow the script recognize that and fix tag of the one member. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260109151219.26206-3-michal.wajdeczko@intel.com
2026-01-12drm/xe/mert: Normalize xe_mert.h include guardsMichal Wajdeczko1-3/+3
Most of our header files are using include guard names with single underscore and we don't use trailing comments on final #endif. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260109151219.26206-2-michal.wajdeczko@intel.com
2026-01-12drm/i915/guc: make 'guc_hw_reg_state' static as it isn't exportedBen Dooks1-1/+1
The guc_hw_reg_state array is not exported, so make it static. Fixes the following sparse warning: drivers/gpu/drm/i915/i915_gpu_error.c:692:3: warning: symbol 'guc_hw_reg_state' was not declared. Should it be static? Fixes: ba391a102ec11 ("drm/i915/guc: Include the GuC registers in the error state") Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260108201202.59250-2-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (cherry picked from commit 701c47493328a8173996e7590733be3493af572f) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-01-12drm/msm: remove some dead codeDan Carpenter1-7/+1
This is supposed to test for integer overflow but it is wrong and unnecessary. The size_add()/mul() macros return SIZE_MAX when there is an integer overflow. This code saves the SIZE_MAX to a u64 and then tests if the result is greater than SIZE_MAX which it never will be. Fortunately, when we try to allocate SIZE_MAX bytes the allocation will fail. We even pass __GFP_NOWARN so the allocation fails harmlessly and quietly. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Fixes: 2e6a8a1fe2b2 ("drm/msm: Add VM_BIND ioctl") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/697596/ Link: https://lore.kernel.org/r/aWAMIhZLxUcecbLd@stanley.mountain Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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