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2025-11-12riscv: dts: Add initial Anlogic DR1V90 SoC device treeJunhui Liu1-0/+100
DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS part and 94,464 LUTs for the PL part. The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible UART controllers. Some basic information of the processor can be obtained by running a simple application from nuclei-sdk [1]: -----Nuclei RISC-V CPU Configuration Information----- MARCHID: 0xc900 MIMPID: 0x20300 ISA: RV64 A B C D F I M P S U MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-Safety-Mechanism DLEN=VLEN/2 ILM: 256 KB has-ecc DLM: 256 KB has-ecc ICACHE: 32 KB(set=256,way=2,lsize=64,ecc=1) DCACHE: 32 KB(set=256,way=2,lsize=64,ecc=1) TLB: MainTLB(set=32,way=2,entry=1,ecc=1) ITLB(entry=8) DTLB(entry=8) IREGION: 0x68000000 128 MB Unit Size Address INFO 64KB 0x68000000 DEBUG 64KB 0x68010000 ECLIC 64KB 0x68020000 TIMER 64KB 0x68030000 PLIC 64MB 0x6c000000 INFO-Detail: mpasize : 0 PPI: 0xf8000000 128 MB -----End of Nuclei CPU INFO----- Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application/baremetal/cpuinfo/main.c [1] Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-12riscv: Add Anlogic SoC famly Kconfig supportJunhui Liu1-0/+5
The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-12riscv: defconfig: enable SPI_FSL_QUADSPI as a moduleAlex Elder1-0/+1
The SpacemiT K1 SoC QSPI IP uses the Freescale driver. Enable it as a module in the default kernel configuration for RISC-V. Acked-by: Paul Walmsley <pjw@kernel.org> # for arch/riscv Signed-off-by: Alex Elder <elder@riscstar.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-12riscv: dts: spacemit: define all missing I2C controller nodesTroy Mitchell1-0/+80
SpacemiT K1 SoC is equipped with a total of nine I2C controllers, ranging from I2C0 to I2C8. Prior to this change, only I2C2 and I2C8 were explicitly defined within the device tree. This patch comprehensively adds the device tree node definitions for I2C controller 0, 1, 4 to 7. The I2C3 node is not added because it belongs exclusively to the secure domain which not used in the linux realm. All newly added I2C nodes are set to "disabled" status by default, allowing future board-specific device tree to enable and configure. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20251105-k1-add-i2c-node-v1-2-d18dae246137@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-11-12riscv: dts: spacemit: reorder i2c2 nodeTroy Mitchell1-13/+13
Reorder the i2c2 node to its correct position according to its register address.This improves the readability and maintainability of the device tree file by adhering to the established ordering convention. No functional change is introduced by this reordering. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20251105-k1-add-i2c-node-v1-1-d18dae246137@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-11-12riscv: dts: spacemit: Add OrangePi R2S board device treeMichael Opdenacker2-0/+91
Add initial device tree support for the OrangePi RV2 board [1], which is marketed as using the Ky X1 SoC but is identical in die and package to the SpacemiT K1 SoC [2]. Enable UART0, to boot into a serial console Two Gigabit Ethernet ports with RGMII interface standard support are enabled, each port is connected to an external Motorcomm YT8531C PHY chip which uses the GPIO for reset control. Enable PDMA. Enable 8 GB eMMC chip for storage. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-R2S.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Signed-off-by: Michael Opdenacker <michael.opdenacker@rootcommit.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251112044426.2351999-3-michael.opdenacker@rootcommit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-11-11riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV FireConor Dooley1-0/+96
The BeagleV Fire has an SD card slot and an ADC connected to the QSPI controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-10Merge tag 'riscv-for-linus-6.18-rc6' of ↵Linus Torvalds2-17/+2
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: - fix broken clang build on versions earlier than 19 and binutils versions earlier than 2.38. (This exposed that we're not properly testing earlier toolchain versions in our linux-next builds and PR submissions. This was fixed for this PR, and is being addressed more generally for -next builds.) - remove some redundant Makefile code - avoid building Canaan Kendryte K210-specific code on targets that don't build for the K210 * tag 'riscv-for-linus-6.18-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fix CONFIG_AS_HAS_INSN for new .insn usage riscv: Remove redundant judgment for the default build target riscv: Build loader.bin exclusively for Canaan K210
2025-11-10Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds3-26/+17
Pull kvm fixes from Paolo Bonzini: "Arm: - Fix trapping regression when no in-kernel irqchip is present - Check host-provided, untrusted ranges and offsets in pKVM - Fix regression restoring the ID_PFR1_EL1 register - Fix vgic ITS locking issues when LPIs are not directly injected Arm selftests: - Correct target CPU programming in vgic_lpi_stress selftest - Fix exposure of SCTLR2_EL2 and ZCR_EL2 in get-reg-list selftest RISC-V: - Fix check for local interrupts on riscv32 - Read HGEIP CSR on the correct cpu when checking for IMSIC interrupts - Remove automatic I/O mapping from kvm_arch_prepare_memory_region() x86: - Inject #UD if the guest attempts to execute SEAMCALL or TDCALL as KVM doesn't support virtualization the instructions, but the instructions are gated only by VMXON. That is, they will VM-Exit instead of taking a #UD and until now this resulted in KVM exiting to userspace with an emulation error. - Unload the "FPU" when emulating INIT of XSTATE features if and only if the FPU is actually loaded, instead of trying to predict when KVM will emulate an INIT (CET support missed the MP_STATE path). Add sanity checks to detect and harden against similar bugs in the future. - Unregister KVM's GALog notifier (for AVIC) when kvm-amd.ko is unloaded. - Use a raw spinlock for svm->ir_list_lock as the lock is taken during schedule(), and "normal" spinlocks are sleepable locks when PREEMPT_RT=y. - Remove guest_memfd bindings on memslot deletion when a gmem file is dying to fix a use-after-free race found by syzkaller. - Fix a goof in the EPT Violation handler where KVM checks the wrong variable when determining if the reported GVA is valid. - Fix and simplify the handling of LBR virtualization on AMD, which was made buggy and unnecessarily complicated by nested VM support Misc: - Update Oliver's email address" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (28 commits) KVM: nSVM: Fix and simplify LBR virtualization handling with nested KVM: nSVM: Always recalculate LBR MSR intercepts in svm_update_lbrv() KVM: SVM: Mark VMCB_LBR dirty when MSR_IA32_DEBUGCTLMSR is updated MAINTAINERS: Switch myself to using kernel.org address KVM: arm64: vgic-v3: Release reserved slot outside of lpi_xa's lock KVM: arm64: vgic-v3: Reinstate IRQ lock ordering for LPI xarray KVM: arm64: Limit clearing of ID_{AA64PFR0,PFR1}_EL1.GIC to userspace irqchip KVM: arm64: Set ID_{AA64PFR0,PFR1}_EL1.GIC when GICv3 is configured KVM: arm64: Make all 32bit ID registers fully writable KVM: VMX: Fix check for valid GVA on an EPT violation KVM: guest_memfd: Remove bindings on memslot deletion when gmem is dying KVM: SVM: switch to raw spinlock for svm->ir_list_lock KVM: SVM: Make avic_ga_log_notifier() local to avic.c KVM: SVM: Unregister KVM's GALog notifier on kvm-amd.ko exit KVM: SVM: Initialize per-CPU svm_data at the end of hardware setup KVM: x86: Call out MSR_IA32_S_CET is not handled by XSAVES KVM: x86: Harden KVM against imbalanced load/put of guest FPU state KVM: x86: Unload "FPU" state on INIT if and only if its currently in-use KVM: arm64: Check the untrusted offset in FF-A memory share KVM: arm64: Check range args for pKVM mem transitions ...
2025-11-09Merge tag 'kvm-riscv-fixes-6.18-2' of https://github.com/kvm-riscv/linux ↵Paolo Bonzini3-26/+17
into HEAD KVM/riscv fixes for 6.18, take #2 - Fix check for local interrupts on riscv32 - Read HGEIP CSR on the correct cpu when checking for IMSIC interrupts - Remove automatic I/O mapping from kvm_arch_prepare_memory_region()
2025-11-08riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3Alex Elder3-0/+43
Define DTS nodes to enable support for QSPI on the K1 SoC, including the pin control configuration used. Enable QSPI on the Banana Pi BPI-F3 board. Signed-off-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/20251027133008.360237-9-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-11-07riscv: Fix CONFIG_AS_HAS_INSN for new .insn usageNathan Chancellor1-1/+1
After commit 44aa25c000b4 ("riscv: asm: use .insn for making custom instructions"), builds using LLVM older that 19 or binutils older than 2.38 fail with: arch/riscv/include/asm/vdso/processor.h: Assembler messages: arch/riscv/include/asm/vdso/processor.h:27: Error: unrecognized opcode `0x100000f' arch/riscv/include/asm/vdso/processor.h:27: Error: unrecognized opcode `0x100000f' arch/riscv/include/asm/vdso/processor.h:27: Error: unrecognized opcode `0x100000f' arch/riscv/include/asm/vdso/processor.h:27: Error: unrecognized opcode `0x100000f' make[4]: *** [scripts/Makefile.build:287: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1 In file included from <built-in>:4: In file included from lib/vdso/gettimeofday.c:6: In file included from include/vdso/datapage.h:21: In file included from include/vdso/processor.h:10: arch/riscv/include/asm/vdso/processor.h:23:2: error: expected instruction format 23 | ALT_RISCV_PAUSE(); | ^ arch/riscv/include/asm/errata_list.h:47:3: note: expanded from macro 'ALT_RISCV_PAUSE' 47 | RISCV_PAUSE, /* Original RISC‑V pause insn */ \ | ^ arch/riscv/include/asm/insn-def.h:259:21: note: expanded from macro 'RISCV_PAUSE' 259 | #define RISCV_PAUSE ASM_INSN_I("0x100000f") | ^ arch/riscv/include/asm/asm.h:16:26: note: expanded from macro 'ASM_INSN_I' 16 | #define ASM_INSN_I(__x) ".insn " __x | ^ <inline asm>:5:7: note: instantiated into assembly here 5 | .insn 0x100000f | ^ binutils gained support for '.insn <value>' in 2.38 [1] and LLVM gained support in 19 [2]. Adjust the test for CONFIG_AS_HAS_INSN to ensure that all versions of .insn are supported before being used. Fixes: 44aa25c000b4 ("riscv: asm: use .insn for making custom instructions") Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a262b82fdbf4cda3b0648b1adc32245ca3f78b7a [1] Link: https://github.com/llvm/llvm-project/commit/2a086dce691e3cc34a2fc27f4fb255bb2cbbfac9 [2] Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://patch.msgid.link/20251107-riscv-fix-new-insn-usage-v1-1-9a186c5928a0@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-11-07riscv: Remove redundant judgment for the default build targetFeng Jiang1-15/+0
The value of KBUILD_IMAGE is derived from $(boot-image-y), so there's no need for redundant checks before this. Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/20251029094429.553842-2-jiangfeng@kylinos.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-11-07riscv: Build loader.bin exclusively for Canaan K210Feng Jiang1-1/+1
According to the explanation in commit ef10bdf9c3e6 ("riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210"), loader.bin is a special feature of the Canaan K210 and is not applicable to other SoCs. Fixes: e79dfcbfb902 ("riscv: make image compression configurable") Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/20251029094429.553842-1-jiangfeng@kylinos.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-11-06riscv: dts: spacemit: add MusePi Pro board device treeTroy Mitchell2-0/+80
Add initial device tree support for the MusePi Pro board [1]. The board is using the SpacemiT K1/M1 SoC. This device tree is adapted from the SpacemiT vendor tree [2] and enables basic board functionality, including UART console, LED, eMMC, Ethernet, and PDMA. Link: https://developer.spacemit.com/documentation?token=YJtdwnvvViPVcmkoPDpcvwfVnrh&type=pdf [1] Link: https://gitee.com/bianbu-linux/linux-6.6/blob/k1-bl-v2.2.y/arch/riscv/boot/dts/spacemit/k1-x_MUSE-Pi-Pro.dts [2] Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20251023-k1-musepi-pro-dts-v4-2-01836303e10f@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-11-05KVM: Rename kvm_arch_vcpu_async_ioctl() to kvm_arch_vcpu_unlocked_ioctl()Sean Christopherson1-2/+2
Rename the "async" ioctl API to "unlocked" so that upcoming usage in x86's TDX code doesn't result in a massive misnomer. To avoid having to retry SEAMCALLs, TDX needs to acquire kvm->lock *and* all vcpu->mutex locks, and acquiring all of those locks after/inside the current vCPU's mutex is a non-starter. However, TDX also needs to acquire the vCPU's mutex and load the vCPU, i.e. the handling is very much not async to the vCPU. No functional change intended. Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Reviewed-by: Yan Zhao <yan.y.zhao@intel.com> Tested-by: Yan Zhao <yan.y.zhao@intel.com> Tested-by: Kai Huang <kai.huang@intel.com> Link: https://patch.msgid.link/20251030200951.3402865-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-11-05KVM: Make support for kvm_arch_vcpu_async_ioctl() mandatorySean Christopherson1-1/+0
Implement kvm_arch_vcpu_async_ioctl() "natively" in x86 and arm64 instead of relying on an #ifdef'd stub, and drop HAVE_KVM_VCPU_ASYNC_IOCTL in anticipation of using the API on x86. Once x86 uses the API, providing a stub for one architecture and having all other architectures opt-in requires more code than simply implementing the API in the lone holdout. Eliminating the Kconfig will also reduce churn if the API is renamed in the future (spoiler alert). No functional change intended. Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Reviewed-by: Yan Zhao <yan.y.zhao@intel.com> Tested-by: Yan Zhao <yan.y.zhao@intel.com> Tested-by: Kai Huang <kai.huang@intel.com> Link: https://patch.msgid.link/20251030200951.3402865-2-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-11-03riscv/uaccess: Use unsafe wrappers for ASM GOTOThomas Gleixner1-4/+4
ASM GOTO is miscompiled by GCC when it is used inside a auto cleanup scope: bool foo(u32 __user *p, u32 val) { scoped_guard(pagefault) unsafe_put_user(val, p, efault); return true; efault: return false; } It ends up leaking the pagefault disable counter in the fault path. clang at least fails the build. Rename unsafe_*_user() to arch_unsafe_*_user() which makes the generic uaccess header wrap it with a local label that makes both compilers emit correct code. Same for the kernel_nofault() variants. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Link: https://patch.msgid.link/20251027083745.419351819@linutronix.de
2025-11-02riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0Chen Wang1-0/+12
Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board, which uses SG2042 SoC. Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/50a753f9b8cbd5a90b5b2df737f87fc77a9b33a7.1760929111.git.unicorn_wang@outlook.com Tested-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-11-02riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.XChen Wang1-0/+12
Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board, which uses SG2042 SoC. Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/1ad96631cc9d9d7403a2bed5585d856fa101a2ef.1760929111.git.unicorn_wang@outlook.com Tested-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-11-02riscv: sophgo: dts: enable PCIe for PioneerBoxChen Wang1-0/+12
Enable PCIe controllers for PioneerBox, which uses SG2042 SoC. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/ec474c5eefb79626dd6a4d65454da9109aaf2f4d.1760929111.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-11-02riscv: sophgo: dts: add PCIe controllers for SG2042Chen Wang1-0/+88
Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/b34d819cd763482e0ecbc5c5ea721f0101d1f844.1760929111.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-10-31riscv: dts: thead: Add reset controllers of more subsystems for TH1520Yao Zi1-0/+37
Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The one for AO subsystem is marked as reserved, since it may be used by AON firmware. Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Yao Zi <ziyao@disroot.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
2025-10-28riscv: dts: thead: Add PWM fan and thermal controlMichal Wilczynski1-0/+67
Add Device Tree nodes to enable a PWM controlled fan and it's associated thermal management for the Lichee Pi 4A board. This enables temperature-controlled active cooling for the Lichee Pi 4A board based on SoC temperature. Reviewed-by: Drew Fustini <fustini@kernel.org> Tested-by: Drew Fustini <fustini@kernel.org> Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <fustini@kernel.org>
2025-10-28riscv: dts: thead: Add PWM controller nodeMichal Wilczynski1-0/+7
Add the Device Tree node for the T-HEAD TH1520 SoC's PWM controller. Reviewed-by: Drew Fustini <fustini@kernel.org> Tested-by: Drew Fustini <fustini@kernel.org> Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <fustini@kernel.org>
2025-10-27riscv: KGDB: Replace deprecated strcpy in kgdb_arch_handle_qxfer_pktThorsten Blum1-2/+2
strcpy() is deprecated because it can cause a buffer overflow when the sizes of the source and the destination are not known at compile time. Use strscpy() instead. Link: https://github.com/KSPP/linux/issues/88 Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://lore.kernel.org/r/20251011004750.461954-1-thorsten.blum@linux.dev Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-27riscv: asm: use .insn for making custom instructionsBen Dooks3-7/+13
The assembler has .insn for building custom instructions now, so change the .4byte to .insn. This ensures the output is marked as an instruction and not as data which may confuse both debuggers and anything else that relies on this sort of marking. Add an ASM_INSN_I() wrapper in asm.h to allow the selecting of how this is output so older assemblers are still good. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Link: https://lore.kernel.org/r/20251024171640.65232-1-ben.dooks@codethink.co.uk Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-27riscv: tests: Make RISCV_KPROBES_KUNIT tristateVivian Wang3-2/+7
This disallows KUNIT=m and RISCV_KPROBES_KUNIT=y, which produces these relocs_check.sh warnings when RELOCATABLE=y: WARNING: 3 bad relocations ffffffff81e24118 R_RISCV_64 kunit_unary_assert_format ffffffff81e24a60 R_RISCV_64 kunit_binary_assert_format ffffffff81e269d0 R_RISCV_JUMP_SLOT __kunit_do_failed_assertion This fixes allmodconfig build. Reported-by: Inochi Amaoto <inochiama@gmail.com> Fixes: f2fab612824f ("riscv: Add kprobes KUnit test") Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Tested-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Nam Cao <namcao@linutronix.de> Link: https://lore.kernel.org/r/20251020-riscv-kunit-kconfig-fix-6-18-v1-2-d773b5d5ce48@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-27riscv: tests: Rename kprobes_test_riscv to kprobes_riscvVivian Wang1-1/+1
According to Documentation/dev-tools/kunit/style.rst a KUnit test suite normally should not have "test" in the name. Rename it to follow the style guide. Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Tested-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Nam Cao <namcao@linutronix.de> Link: https://lore.kernel.org/r/20251020-riscv-kunit-kconfig-fix-6-18-v1-1-d773b5d5ce48@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-27riscv: Fix memory leak in module_frob_arch_sections()Miaoqian Lin1-2/+6
The current code directly overwrites the scratch pointer with the return value of kvrealloc(). If kvrealloc() fails and returns NULL, the original buffer becomes unreachable, causing a memory leak. Fix this by using a temporary variable to store kvrealloc()'s return value and only update the scratch pointer on success. Found via static anlaysis and this is similar to commit 42378a9ca553 ("bpf, verifier: Fix memory leak in array reallocation for stack state") Fixes: be17c0df6795 ("riscv: module: Optimize PLT/GOT entry counting") Cc: stable@vger.kernel.org Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20251026091912.39727-1-linmq006@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-27riscv: ptdump: use seq_puts() in pt_dump_seq_puts() macroJosephine Pfeiffer1-1/+1
The pt_dump_seq_puts() macro incorrectly uses seq_printf() instead of seq_puts(). This is both a performance issue and conceptually wrong, as the macro name suggests plain string output (puts) but the implementation uses formatted output (printf). The macro is used in ptdump.c:301 to output a newline character. Using seq_printf() adds unnecessary overhead for format string parsing when outputting this constant string. This bug was introduced in commit 59c4da8640cc ("riscv: Add support to dump the kernel page tables") in 2020, which copied the implementation pattern from other architectures that had the same bug. Fixes: 59c4da8640cc ("riscv: Add support to dump the kernel page tables") Signed-off-by: Josephine Pfeiffer <hi@josie.lol> Link: https://lore.kernel.org/r/20251018170451.3355496-1-hi@josie.lol Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-27riscv: stacktrace: Disable KASAN checks for non-current tasksChunyan Zhang1-2/+19
Unwinding the stack of a task other than current, KASAN would report "BUG: KASAN: out-of-bounds in walk_stackframe+0x41c/0x460" There is a same issue on x86 and has been resolved by the commit 84936118bdf3 ("x86/unwind: Disable KASAN checks for non-current tasks") The solution could be applied to RISC-V too. This patch also can solve the issue: https://seclists.org/oss-sec/2025/q4/23 Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly") Co-developed-by: Jiakai Xu <xujiakai2025@iscas.ac.cn> Signed-off-by: Jiakai Xu <xujiakai2025@iscas.ac.cn> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn> Link: https://lore.kernel.org/r/20251022072608.743484-1-zhangchunyan@iscas.ac.cn [pjw@kernel.org: clean up checkpatch issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-24RISC-V: KVM: Remove automatic I/O mapping for VM_PFNMAPFangyu Yu1-23/+2
As of commit aac6db75a9fc ("vfio/pci: Use unmap_mapping_range()"), vm_pgoff may no longer guaranteed to hold the PFN for VM_PFNMAP regions. Using vma->vm_pgoff to derive the HPA here may therefore produce incorrect mappings. Instead, I/O mappings for such regions can be established on-demand during g-stage page faults, making the upfront ioremap in this path is unnecessary. Fixes: aac6db75a9fc ("vfio/pci: Use unmap_mapping_range()") Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251021142131.78796-1-fangyu.yu@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-24riscv: dts: spacemit: add Ethernet and PDMA to OrangePi RV2Michael Opdenacker1-0/+52
The OrangePi RV2 board ships two RGMII ethernet ports. Each has an external Motorcomm YT8531C PHY attached, the PHY uses GPIO for reset pin control. Enable PDMA for the SpacemiT K1-based SoC in the OrangePi RV2 board. Signed-off-by: Michael Opdenacker <michael.opdenacker@rootcommit.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251022201807.1474789-2-michael.opdenacker@rootcommit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-20dts: starfive: jh7110-common: split out mmc0 reset pins from common into boardsE Shattow6-11/+65
Prepare for Orange Pi RV using jh7110-common.dtsi having GPIO62 assignment different than mmc0 reset by splitting this out into each board dts. Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-10-18riscv: defconfig: Enable Tenstorrent SoCsDrew Fustini1-0/+1
Enable support for Tenstorrent SoCs in the default configuration. Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com> Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
2025-10-18riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCsDrew Fustini1-0/+8
Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the Blackhole. Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com> Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
2025-10-18riscv: dts: Add Tenstorrent Blackhole SoC PCIe cardsDrew Fustini4-0/+125
Add device tree source describing the Tenstorrent Blackhole SoC and the Blackhole P100 and P150 PCIe cards. There are no differences between the P100 and P150 cards from the perspective of an OS kernel like Linux running on the X280 cores. There is a virtual UART implemented in OpenSBI firmware that allows a console program on the PCIe host to communicate through shared memory with Linux running on the Blackhole card. CONFIG_HVC_RISCV_SBI needs to be enabled. The boot script on the host adds 'console=hvc0' so that the full boot output appears in the console program on the host. Link: https://github.com/tenstorrent/opensbi/ Link: https://github.com/tenstorrent/tt-bh-linux Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com> Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
2025-10-18riscv: hwprobe: avoid uninitialized variable use in hwprobe_arch_id()Paul Walmsley1-0/+6
Resolve this smatch warning: arch/riscv/kernel/sys_hwprobe.c:50 hwprobe_arch_id() error: uninitialized symbol 'cpu_id'. This could happen if hwprobe_arch_id() was called with a key ID of something other than MVENDORID, MIMPID, and MARCHID. This does not happen in the current codebase. The only caller of hwprobe_arch_id() is a function that only passes one of those three key IDs. For the sake of reducing static analyzer warning noise, and in the unlikely event that hwprobe_arch_id() is someday called with some other key ID, validate hwprobe_arch_id()'s input to ensure that 'cpu_id' is always initialized before use. Fixes: ea3de9ce8aa280 ("RISC-V: Add a syscall for HW probing") Cc: Evan Green <evan@rivosinc.com> Signed-off-by: Paul Walmsley <pjw@kernel.org> Link: https://lore.kernel.org/r/cf5a13ec-19d0-9862-059b-943f36107bf3@kernel.org
2025-10-18riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()Paul Walmsley1-2/+2
In has_thead_homogeneous_vlenb(), smatch detected that the vlenb variable could be used while uninitialized. It appears that this could happen if no CPUs described in DT have the "thead,vlenb" property. Fix by initializing vlenb to 0, which will keep thead_vlenb_of set to 0 (as it was statically initialized). This in turn will cause riscv_v_setup_vsize() to fall back to CSR probing - the desired result if thead,vlenb isn't provided in the DT data. While here, fix a nearby comment typo. Cc: stable@vger.kernel.org Cc: Charlie Jenkins <charlie@rivosinc.com> Fixes: 377be47f90e41 ("riscv: vector: Use vlenb from DT for thead") Signed-off-by: Paul Walmsley <pjw@kernel.org> Link: https://lore.kernel.org/r/22674afb-2fe8-2a83-1818-4c37bd554579@kernel.org
2025-10-17riscv: hwprobe: Fix stale vDSO data for late-initialized keys at bootJingwei Wang5-15/+79
The hwprobe vDSO data for some keys, like MISALIGNED_VECTOR_PERF, is determined by an asynchronous kthread. This can create a race condition where the kthread finishes after the vDSO data has already been populated, causing userspace to read stale values. To fix this race, a new 'ready' flag is added to the vDSO data, initialized to 'false' during arch_initcall_sync. This flag is checked by both the vDSO's user-space code and the riscv_hwprobe syscall. The syscall serves as a one-time gate, using a completion to wait for any pending probes before populating the data and setting the flag to 'true', thus ensuring userspace reads fresh values on its first request. Reported-by: Tsukasa OI <research_trasio@irq.a4lg.com> Closes: https://lore.kernel.org/linux-riscv/760d637b-b13b-4518-b6bf-883d55d44e7f@irq.a4lg.com/ Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alexandre Ghiti <alexghiti@rivosinc.com> Cc: Olof Johansson <olof@lixom.net> Cc: stable@vger.kernel.org Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Co-developed-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Jingwei Wang <wangjingwei@iscas.ac.cn> Link: https://lore.kernel.org/r/20250811142035.105820-1-wangjingwei@iscas.ac.cn [pjw@kernel.org: fix checkpatch issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17riscv: add a forward declaration for cpuinfo_opPaul Walmsley1-0/+2
Add a forward declaration for cpuinfo_op to resolve a sparse warning. Link: https://lore.kernel.org/r/b831f349-5d0c-f7ac-8362-acb20bc6221a@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17RISC-V: Don't print details of CPUs disabled in DTAnup Patel1-3/+1
Early boot stages may disable CPU DT nodes for unavailable CPUs based on SKU, pinstraps, eFuse, etc. Currently, the riscv_early_of_processor_hartid() prints details of a CPU if it is disabled in DT which has no value and gives a false impression to the users that there some issue with the CPU. Fixes: e3d794d555cd ("riscv: treat cpu devicetree nodes without status as enabled") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20251014163009.182381-1-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17riscv: Remove the PER_CPU_OFFSET_SHIFT macroSamuel Holland1-7/+1
__per_cpu_offset is an array of unsigned long, so we can reuse the existing RISCV_LGPTR macro. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20251015225604.3860409-1-samuel.holland@sifive.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17riscv: mm: Define MAX_POSSIBLE_PHYSMEM_BITS for zsmallocSamuel Holland1-0/+2
This definition is used by zsmalloc to optimize memory allocation. On riscv64, it is the same as MAX_PHYSMEM_BITS from asm/sparsemem.h, but that definition depends on CONFIG_SPARSEMEM. The correct definition is already provided for riscv32. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20251015233327.3885003-1-samuel.holland@sifive.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17riscv: Register IPI IRQs with unique namesSamuel Holland1-12/+12
This allows different IPIs to be distinguished in tracing output. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20251016003244.3910332-1-samuel.holland@sifive.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17RISC-V: Define pgprot_dmacoherent() for non-coherent devicesAnup Patel1-0/+2
The pgprot_dmacoherent() is used when allocating memory for non-coherent devices and by default pgprot_dmacoherent() is same as pgprot_noncached() unless architecture overrides it. Currently, there is no pgprot_dmacoherent() definition for RISC-V hence non-coherent device memory is being mapped as IO thereby making CPU access to such memory slow. Define pgprot_dmacoherent() to be same as pgprot_writecombine() for RISC-V so that CPU access non-coherent device memory as NOCACHE which is better than accessing it as IO. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Han Gao <rabenda.cn@gmail.com> Tested-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Link: https://lore.kernel.org/r/20250820152316.1012757-1-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-10-17riscv: dts: thead: add zfh for th1520Han Gao1-4/+4
th1520 support Zfh ISA extension. It supports the same RISC-V extensions as SG2042. commit cb074bed1186 ("riscv: dts: sophgo: add zfh for sg2042") Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
2025-10-17riscv: dts: thead: add ziccrse for th1520Han Gao1-8/+16
Existing rv64 hardware conforms to the rva20 profile. Ziccrse is an additional extension required by the rva20 profile, so th1520 has this extension. Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
2025-10-17riscv: dts: thead: add xtheadvector to the th1520 devicetreeHan Gao1-4/+8
The th1520 support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. This can be tested by passing the "mitigations=off" kernel parameter. Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
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